1 /*
2 * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/kernel.h>
8 #include <esp_heap_caps.h>
9
10 #include <stdlib.h>
11 #include <ctype.h>
12 #include "sdkconfig.h"
13 #include "esp_types.h"
14 #include "esp_log.h"
15 #include "soc/rtc_periph.h"
16 #include "soc/syscon_periph.h"
17 #include "soc/rtc.h"
18 #include "soc/periph_defs.h"
19 #include "esp_intr_alloc.h"
20 #include "sys/lock.h"
21 #include "esp_private/rtc_ctrl.h"
22 #include "esp_attr.h"
23
24 #ifndef NDEBUG
25 // Enable built-in checks in queue.h in debug builds
26 #define INVARIANTS
27 #endif
28 #include "sys/queue.h"
29
30 #if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
31 static const char *TAG = "rtc_module";
32 #endif
33
34 #if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
35
36 #define NOT_REGISTERED (-1)
37
38 int rtc_spinlock;
39 static DRAM_ATTR int s_rtc_isr_handler_list_lock;
40 #define RTC_ISR_HANDLER_ENTER_CRITICAL() do { s_rtc_isr_handler_list_lock = irq_lock(); } while(0)
41 #define RTC_ISR_HANDLER_EXIT_CRITICAL() irq_unlock(s_rtc_isr_handler_list_lock);
42
43 // Disable the interrupt which cannot work without cache.
44 static DRAM_ATTR uint32_t rtc_intr_cache;
45 static DRAM_ATTR uint32_t rtc_intr_enabled;
46 static DRAM_ATTR int rtc_isr_cpu = NOT_REGISTERED; // Unused number
47 static void s_rtc_isr_noniram_hook(uint32_t rtc_intr_mask);
48 static void s_rtc_isr_noniram_hook_relieve(uint32_t rtc_intr_mask);
49
50 /*---------------------------------------------------------------
51 INTERRUPT HANDLER
52 ---------------------------------------------------------------*/
53
54
55 typedef struct rtc_isr_handler_ {
56 uint32_t mask;
57 intr_handler_t handler;
58 void* handler_arg;
59 uint32_t flags;
60 SLIST_ENTRY(rtc_isr_handler_) next;
61 } rtc_isr_handler_t;
62
63 static DRAM_ATTR SLIST_HEAD(rtc_isr_handler_list_, rtc_isr_handler_) s_rtc_isr_handler_list =
64 SLIST_HEAD_INITIALIZER(s_rtc_isr_handler_list);
65 static intr_handle_t s_rtc_isr_handle;
66
rtc_isr(void * arg)67 IRAM_ATTR static void rtc_isr(void* arg)
68 {
69 uint32_t status = REG_READ(RTC_CNTL_INT_ST_REG);
70 rtc_isr_handler_t* it;
71 RTC_ISR_HANDLER_ENTER_CRITICAL();
72 SLIST_FOREACH(it, &s_rtc_isr_handler_list, next) {
73 if (it->mask & status) {
74 RTC_ISR_HANDLER_EXIT_CRITICAL();
75 (*it->handler)(it->handler_arg);
76 RTC_ISR_HANDLER_ENTER_CRITICAL();
77 }
78 }
79 RTC_ISR_HANDLER_EXIT_CRITICAL();
80 REG_WRITE(RTC_CNTL_INT_CLR_REG, status);
81 }
82
rtc_isr_ensure_installed(void)83 static esp_err_t rtc_isr_ensure_installed(void)
84 {
85 esp_err_t err = ESP_OK;
86 RTC_ISR_HANDLER_ENTER_CRITICAL();
87 if (s_rtc_isr_handle) {
88 goto out;
89 }
90
91 REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
92 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
93 err = esp_intr_alloc(ETS_RTC_CORE_INTR_SOURCE, ESP_INTR_FLAG_IRAM, &rtc_isr, NULL, &s_rtc_isr_handle);
94 if (err != ESP_OK) {
95 goto out;
96 }
97 rtc_isr_cpu = esp_intr_get_cpu(s_rtc_isr_handle);
98 out:
99 RTC_ISR_HANDLER_EXIT_CRITICAL();
100 return err;
101 }
102 #endif // !CONFIG_IDF_TARGET_ESP32C6 TODO: IDF-5645
103
rtc_isr_register(intr_handler_t handler,void * handler_arg,uint32_t rtc_intr_mask,uint32_t flags)104 esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg, uint32_t rtc_intr_mask, uint32_t flags)
105 {
106 #if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
107 ESP_EARLY_LOGW(TAG, "rtc_isr_register() has not been implemented yet");
108 return ESP_OK;
109 #else
110 esp_err_t err = rtc_isr_ensure_installed();
111 if (err != ESP_OK) {
112 return err;
113 }
114
115 rtc_isr_handler_t* item = heap_caps_malloc(sizeof(*item), MALLOC_CAP_INTERNAL);
116 if (item == NULL) {
117 return ESP_ERR_NO_MEM;
118 }
119 item->handler = handler;
120 item->handler_arg = handler_arg;
121 item->mask = rtc_intr_mask;
122 item->flags = flags;
123 RTC_ISR_HANDLER_ENTER_CRITICAL();
124 if (flags & RTC_INTR_FLAG_IRAM) {
125 s_rtc_isr_noniram_hook(rtc_intr_mask);
126 } else {
127 s_rtc_isr_noniram_hook_relieve(rtc_intr_mask);
128 }
129 SLIST_INSERT_HEAD(&s_rtc_isr_handler_list, item, next);
130 RTC_ISR_HANDLER_EXIT_CRITICAL();
131 return ESP_OK;
132 #endif
133 }
134
rtc_isr_deregister(intr_handler_t handler,void * handler_arg)135 esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg)
136 {
137 #if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
138 ESP_EARLY_LOGW(TAG, "rtc_isr_deregister() has not been implemented yet");
139 return ESP_OK;
140 #else
141 rtc_isr_handler_t* it;
142 rtc_isr_handler_t* prev = NULL;
143 bool found = false;
144 RTC_ISR_HANDLER_ENTER_CRITICAL();
145 SLIST_FOREACH(it, &s_rtc_isr_handler_list, next) {
146 if (it->handler == handler && it->handler_arg == handler_arg) {
147 if (it == SLIST_FIRST(&s_rtc_isr_handler_list)) {
148 SLIST_REMOVE_HEAD(&s_rtc_isr_handler_list, next);
149 } else {
150 SLIST_REMOVE_AFTER(prev, next);
151 }
152 found = true;
153 if (it->flags & RTC_INTR_FLAG_IRAM) {
154 s_rtc_isr_noniram_hook_relieve(it->mask);
155 }
156 free(it);
157 break;
158 }
159 prev = it;
160 }
161 RTC_ISR_HANDLER_EXIT_CRITICAL();
162 return found ? ESP_OK : ESP_ERR_INVALID_STATE;
163 #endif
164 }
165
166 #if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
167 /**
168 * @brief This helper function can be used to avoid the interrupt to be triggered with cache disabled.
169 * There are lots of different signals on RTC module (i.e. sleep_wakeup, wdt, brownout_detect, etc.)
170 * We might want some of them can be triggered with cache disabled, some are not. Therefore, this function
171 * is created to avoid those which do not want to be triggered with cache disabled.
172 *
173 * @param rtc_intr_mask the mask of the rtc interrupt.
174 */
s_rtc_isr_noniram_hook(uint32_t rtc_intr_mask)175 static void s_rtc_isr_noniram_hook(uint32_t rtc_intr_mask)
176 {
177 rtc_intr_cache |= rtc_intr_mask;
178 }
179
s_rtc_isr_noniram_hook_relieve(uint32_t rtc_intr_mask)180 static void s_rtc_isr_noniram_hook_relieve(uint32_t rtc_intr_mask)
181 {
182 rtc_intr_cache &= ~rtc_intr_mask;
183 }
184 #endif
185
186
rtc_isr_noniram_disable(uint32_t cpu)187 IRAM_ATTR void rtc_isr_noniram_disable(uint32_t cpu)
188 {
189 #if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
190 if (rtc_isr_cpu == cpu) {
191 rtc_intr_enabled |= RTCCNTL.int_ena.val;
192 RTCCNTL.int_ena.val &= rtc_intr_cache;
193 }
194 #endif
195 }
196
rtc_isr_noniram_enable(uint32_t cpu)197 IRAM_ATTR void rtc_isr_noniram_enable(uint32_t cpu)
198 {
199 #if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
200 if (rtc_isr_cpu == cpu) {
201 RTCCNTL.int_ena.val = rtc_intr_enabled;
202 rtc_intr_enabled = 0;
203 }
204 #endif
205 }
206
