1 /*
2  * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <stdint.h>
8 #include <stdlib.h>
9 #include "esp_attr.h"
10 #include "soc/soc.h"
11 #include "soc/rtc.h"
12 #include "soc/rtc_cntl_reg.h"
13 #include "soc/syscon_reg.h"
14 #include "soc/bb_reg.h"
15 #include "soc/nrx_reg.h"
16 #include "soc/fe_reg.h"
17 #include "soc/timer_group_reg.h"
18 #include "soc/system_reg.h"
19 #include "esp32c2/rom/ets_sys.h"
20 #include "esp32c2/rom/rtc.h"
21 #include "regi2c_ctrl.h"
22 #include "soc/regi2c_lp_bias.h"
23 #include "soc/regi2c_dig_reg.h"
24 
25 static const DRAM_ATTR rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
26 
27 /**
28  * Configure whether certain peripherals are powered down in deep sleep
29  * @param cfg power down flags as rtc_sleep_pu_config_t structure
30  */
rtc_sleep_pu(rtc_sleep_pu_config_t cfg)31 void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
32 {
33     REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
34     REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
35     REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
36     REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
37     REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
38     REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
39     REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
40     REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu);
41     REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
42     REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
43     REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
44     if (cfg.sram_fpu) {
45         REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
46     } else {
47         REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0);
48     }
49     if (cfg.rom_ram_fpu) {
50         REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, SYSCON_ROM_POWER_UP);
51     } else {
52         REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0);
53     }
54 }
55 
rtc_sleep_get_default_config(uint32_t sleep_flags,rtc_sleep_config_t * out_config)56 void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config)
57 {
58     *out_config = (rtc_sleep_config_t) {
59         .lslp_mem_inf_fpu = 1,
60         .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0,
61         .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0,
62         .wdt_flashboot_mod_en = 0,
63         .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0,
64         .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1,
65         .deep_slp_reject = 1,
66         .light_slp_reject = 1,
67     };
68     if (sleep_flags & RTC_SLEEP_PD_DIG) {
69         assert(sleep_flags & RTC_SLEEP_PD_XTAL);
70         if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)) {
71             /*
72              * dbg_att_slp need to set to 0: rtc voltage is about 0.98v
73              * support all features:
74              * - 8MD256 as RTC slow clock src
75              * - RTC IO as input
76              */
77             out_config->rtc_regulator_fpu = 1;
78             out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP;
79             out_config->rtc_dbias_slp = 0;
80         } else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) {
81             /*
82              * Default mode
83              * rtc voltage in sleep need stable and not less than 0.7v
84              * support features:
85              * - RTC IO as input
86              */
87             out_config->rtc_regulator_fpu = 1;
88             out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
89             out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7;
90         } else {
91             /*
92              * rtc regulator not opened and rtc voltage is about 0.66v (ultra low power):
93              * not support features:
94              * - 8MD256 as RTC slow clock src
95              * - RTC IO as input
96              */
97             out_config->rtc_regulator_fpu = 0;
98             out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
99             out_config->rtc_dbias_slp = 0;
100         }
101     } else {
102         out_config->rtc_regulator_fpu = 1;
103         // rtc & digital voltage from high to low
104         if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) {
105             /*
106              * digital voltage need to be >= 1.1v
107              * Support all features:
108              * - XTAL
109              * - RC 8M used by digital system
110              * - 8MD256 as RTC slow clock src (only need dbg_atten_slp set to 0)
111              */
112             out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
113             out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10;
114             out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V10;
115         } else if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)){
116             /*
117              * dbg_att_slp need to set to 0: digital voltage is about 0.64v & rtc voltage is 0.98v
118              * Support features:
119              * - 8MD256 as RTC slow clock src
120             */
121             out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
122             out_config->dig_dbias_slp = 0;
123             out_config->rtc_dbias_slp = 0;
124         } else {
125             /*
126              * digital voltage not less than 0.6v.
127              * not support features:
128              * - XTAL
129              * - RC 8M used by digital system
130              * - 8MD256 as RTC slow clock src
131             */
132             out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT;
133             out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6;
134             out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6;
135         }
136     }
137     if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) {
138         out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON;
139         out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON;
140     } else {
141         out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
142         out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
143     }
144 }
145 
rtc_sleep_init(rtc_sleep_config_t cfg)146 void rtc_sleep_init(rtc_sleep_config_t cfg)
147 {
148     if (cfg.lslp_mem_inf_fpu) {
149         rtc_sleep_pu(pu_cfg);
150     }
151 
152     assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp);
153     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp);
154     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp);
155 
156     REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT);
157     REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT);
158     REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT);
159     REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp);
160     REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp);
161     REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp);
162 
163     if (cfg.deep_slp) {
164         REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
165         SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
166         CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
167                             RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
168                             RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
169         CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
170     } else {
171         SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
172         REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
173         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
174     }
175     REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu);
176 
177     if (!cfg.int_8m_pd_en) {
178         SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
179         SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
180     } else {
181         CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
182         CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
183     }
184 
185     /* enable VDDSDIO control by state machine */
186     REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_VDD_SPI_PWR_FORCE);
187     REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_VDD_SPI_PD_EN, cfg.vddsdio_pd_en);
188 
189     REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
190     REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
191 
192     REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
193     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
194 }
195 
rtc_sleep_low_init(uint32_t slowclk_period)196 void rtc_sleep_low_init(uint32_t slowclk_period)
197 {
198     // set 5 PWC state machine times to fit in main state machine time
199     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
200     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
201     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
202 }
203 
204 static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);
205 
rtc_sleep_start(uint32_t wakeup_opt,uint32_t reject_opt,uint32_t lslp_mem_inf_fpu)206 uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
207 {
208     REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
209     REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
210 
211     SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
212                       RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
213 
214     /* Start entry into sleep mode */
215     SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
216 
217     while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG,
218                              RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) {
219         ;
220     }
221 
222     return rtc_sleep_finish(lslp_mem_inf_fpu);
223 }
224 
rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)225 static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
226 {
227     /* In deep sleep mode, we never get here */
228     uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW);
229     SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
230                       RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
231 
232     /* restore config if it is a light sleep */
233     if (lslp_mem_inf_fpu) {
234         rtc_sleep_pu(pu_cfg);
235     }
236     return reject;
237 }
238