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Searched refs:MXC_I2S (Results 1 – 18 of 18) sorted by relevance

/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/I2S/
Di2s_me18.c48 int retval = MXC_I2S_RevA_Init((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_Init()
50 MXC_I2S->ctrl1ch0 |= MXC_F_I2S_CTRL1CH0_CLKSEL | MXC_F_I2S_CTRL1CH0_EN; in MXC_I2S_Init()
57 MXC_I2S_RevA_Shutdown((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_Shutdown()
67 return MXC_I2S_RevA_ConfigData((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_ConfigData()
72 MXC_I2S_RevA_TXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXEnable()
77 MXC_I2S_RevA_TXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXDisable()
82 MXC_I2S_RevA_RXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXEnable()
87 MXC_I2S_RevA_RXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXDisable()
92 return MXC_I2S_RevA_SetRXThreshold((mxc_i2s_reva_regs_t *)MXC_I2S, threshold); in MXC_I2S_SetRXThreshold()
97 return MXC_I2S_RevA_SetFrequency((mxc_i2s_reva_regs_t *)MXC_I2S, mode, clkdiv); in MXC_I2S_SetFrequency()
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Di2s_ai85.c46 return MXC_I2S_RevA_Init((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_Init()
51 MXC_I2S_RevA_Shutdown((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_Shutdown()
61 return MXC_I2S_RevA_ConfigData((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_ConfigData()
66 MXC_I2S_RevA_TXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXEnable()
71 MXC_I2S_RevA_TXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXDisable()
76 MXC_I2S_RevA_RXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXEnable()
81 MXC_I2S_RevA_RXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXDisable()
86 return MXC_I2S_RevA_SetRXThreshold((mxc_i2s_reva_regs_t *)MXC_I2S, threshold); in MXC_I2S_SetRXThreshold()
91 return MXC_I2S_RevA_SetFrequency((mxc_i2s_reva_regs_t *)MXC_I2S, mode, clkdiv); in MXC_I2S_SetFrequency()
96 return MXC_I2S_RevA_SetSampleRate((mxc_i2s_reva_regs_t *)MXC_I2S, smpl_rate, smpl_sz, i2s_clk); in MXC_I2S_SetSampleRate()
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Di2s_ai87.c46 return MXC_I2S_RevA_Init((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_Init()
51 MXC_I2S_RevA_Shutdown((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_Shutdown()
61 return MXC_I2S_RevA_ConfigData((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_ConfigData()
66 MXC_I2S_RevA_TXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXEnable()
71 MXC_I2S_RevA_TXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXDisable()
76 MXC_I2S_RevA_RXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXEnable()
81 MXC_I2S_RevA_RXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXDisable()
86 return MXC_I2S_RevA_SetRXThreshold((mxc_i2s_reva_regs_t *)MXC_I2S, threshold); in MXC_I2S_SetRXThreshold()
91 return MXC_I2S_RevA_SetFrequency((mxc_i2s_reva_regs_t *)MXC_I2S, mode, clkdiv); in MXC_I2S_SetFrequency()
96 return MXC_I2S_RevA_SetSampleRate((mxc_i2s_reva_regs_t *)MXC_I2S, smpl_rate, smpl_sz, i2s_clk); in MXC_I2S_SetSampleRate()
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Di2s_me12.c48 return MXC_I2S_RevA_Init((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_Init()
53 MXC_I2S_RevA_Shutdown((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_Shutdown()
63 return MXC_I2S_RevA_ConfigData((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_ConfigData()
68 MXC_I2S_RevA_TXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXEnable()
73 MXC_I2S_RevA_TXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXDisable()
78 MXC_I2S_RevA_RXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXEnable()
83 MXC_I2S_RevA_RXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXDisable()
88 return MXC_I2S_RevA_SetRXThreshold((mxc_i2s_reva_regs_t *)MXC_I2S, threshold); in MXC_I2S_SetRXThreshold()
93 return MXC_I2S_RevA_SetFrequency((mxc_i2s_reva_regs_t *)MXC_I2S, mode, clkdiv); in MXC_I2S_SetFrequency()
98 return MXC_I2S_RevA_SetSampleRate((mxc_i2s_reva_regs_t *)MXC_I2S, smpl_rate, smpl_sz, in MXC_I2S_SetSampleRate()
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Di2s_me15.c42 return MXC_I2S_RevA_Init((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_Init()
47 MXC_I2S_RevA_Shutdown((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_Shutdown()
57 return MXC_I2S_RevA_ConfigData((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_ConfigData()
62 MXC_I2S_RevA_TXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXEnable()
67 MXC_I2S_RevA_TXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXDisable()
72 MXC_I2S_RevA_RXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXEnable()
77 MXC_I2S_RevA_RXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXDisable()
82 return MXC_I2S_RevA_SetRXThreshold((mxc_i2s_reva_regs_t *)MXC_I2S, threshold); in MXC_I2S_SetRXThreshold()
87 return MXC_I2S_RevA_SetFrequency((mxc_i2s_reva_regs_t *)MXC_I2S, mode, clkdiv); in MXC_I2S_SetFrequency()
92 return MXC_I2S_RevA_SetSampleRate((mxc_i2s_reva_regs_t *)MXC_I2S, smpl_rate, smpl_sz, in MXC_I2S_SetSampleRate()
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Di2s_me20.c49 return MXC_I2S_RevA_Init((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_Init()
54 MXC_I2S_RevA_Shutdown((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_Shutdown()
64 return MXC_I2S_RevA_ConfigData((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_ConfigData()
69 MXC_I2S_RevA_TXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXEnable()
74 MXC_I2S_RevA_TXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXDisable()
79 MXC_I2S_RevA_RXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXEnable()
84 MXC_I2S_RevA_RXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXDisable()
89 return MXC_I2S_RevA_SetRXThreshold((mxc_i2s_reva_regs_t *)MXC_I2S, threshold); in MXC_I2S_SetRXThreshold()
94 return MXC_I2S_RevA_SetFrequency((mxc_i2s_reva_regs_t *)MXC_I2S, mode, clkdiv); in MXC_I2S_SetFrequency()
99 return MXC_I2S_RevA_SetSampleRate((mxc_i2s_reva_regs_t *)MXC_I2S, smpl_rate, smpl_sz, in MXC_I2S_SetSampleRate()
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Di2s_me21.c42 return MXC_I2S_RevA_Init((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_Init()
47 MXC_I2S_RevA_Shutdown((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_Shutdown()
57 return MXC_I2S_RevA_ConfigData((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_ConfigData()
62 MXC_I2S_RevA_TXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXEnable()
67 MXC_I2S_RevA_TXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXDisable()
72 MXC_I2S_RevA_RXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXEnable()
77 MXC_I2S_RevA_RXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXDisable()
82 return MXC_I2S_RevA_SetRXThreshold((mxc_i2s_reva_regs_t *)MXC_I2S, threshold); in MXC_I2S_SetRXThreshold()
87 return MXC_I2S_RevA_SetFrequency((mxc_i2s_reva_regs_t *)MXC_I2S, mode, clkdiv); in MXC_I2S_SetFrequency()
92 return MXC_I2S_RevA_SetSampleRate((mxc_i2s_reva_regs_t *)MXC_I2S, smpl_rate, smpl_sz, in MXC_I2S_SetSampleRate()
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Di2s_me17.c52 return MXC_I2S_RevA_Init((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_Init()
57 MXC_I2S_RevA_Shutdown((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_Shutdown()
67 return MXC_I2S_RevA_ConfigData((mxc_i2s_reva_regs_t *)MXC_I2S, req); in MXC_I2S_ConfigData()
84 MXC_I2S->ctrl1ch0 |= MXC_F_I2S_CTRL1CH0_EXTCLK_EN; in MXC_I2S_SelectClockSource()
88 MXC_I2S->ctrl1ch0 &= ~MXC_F_I2S_CTRL1CH0_EXTCLK_EN; in MXC_I2S_SelectClockSource()
99 MXC_I2S_RevA_TXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXEnable()
104 MXC_I2S_RevA_TXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_TXDisable()
109 MXC_I2S_RevA_RXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXEnable()
114 MXC_I2S_RevA_RXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_RXDisable()
119 return MXC_I2S_RevA_SetRXThreshold((mxc_i2s_reva_regs_t *)MXC_I2S, threshold); in MXC_I2S_SetRXThreshold()
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Di2s_me16.c92 return MXC_I2S_RevA_SetSampleRate((mxc_i2s_reva_regs_t *)MXC_I2S, smpl_rate, smpl_sz, in MXC_I2S_SetSampleRate()
98 return MXC_I2S_RevA_GetSampleRate((mxc_i2s_reva_regs_t *)MXC_I2S, ERFO_FREQ); in MXC_I2S_GetSampleRate()
103 return MXC_I2S_RevA_CalculateClockDiv((mxc_i2s_reva_regs_t *)MXC_I2S, smpl_rate, smpl_sz, in MXC_I2S_CalculateClockDiv()
114 return MXC_I2S_RevA_FillTXFIFO((mxc_i2s_reva_regs_t *)MXC_I2S, txData, wordSize, len, smpl_cnt); in MXC_I2S_FillTXFIFO()
119 return MXC_I2S_RevA_ReadRXFIFO((mxc_i2s_reva_regs_t *)MXC_I2S, rxData, wordSize, len, smpl_cnt); in MXC_I2S_ReadRXFIFO()
144 return MXC_I2S_RevA_Transaction((mxc_i2s_reva_regs_t *)MXC_I2S, i2s_req); in MXC_I2S_Transaction()
149 return MXC_I2S_RevA_TransactionAsync((mxc_i2s_reva_regs_t *)MXC_I2S, i2s_req); in MXC_I2S_TransactionAsync()
164 MXC_I2S_RevA_Handler((mxc_i2s_reva_regs_t *)MXC_I2S); in MXC_I2S_Handler()
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Include/
Dmax32662.h473 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) macro
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Include/
Dmax32670.h499 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) macro
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Include/
Dmax32672.h535 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) macro
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Include/
Dmax32675.h498 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) macro
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Include/
Dmax78002.h655 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) macro
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Include/
Dmax78000.h660 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) macro
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/
Dmax32680.h654 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) macro
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/
Dmax32655.h660 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) macro
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/
Dmax32690.h827 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) macro