1 /****************************************************************************** 2 * 3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 4 * Analog Devices, Inc.), 5 * Copyright (C) 2023-2024 Analog Devices, Inc. 6 * 7 * Licensed under the Apache License, Version 2.0 (the "License"); 8 * you may not use this file except in compliance with the License. 9 * You may obtain a copy of the License at 10 * 11 * http://www.apache.org/licenses/LICENSE-2.0 12 * 13 * Unless required by applicable law or agreed to in writing, software 14 * distributed under the License is distributed on an "AS IS" BASIS, 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 * See the License for the specific language governing permissions and 17 * limitations under the License. 18 * 19 ******************************************************************************/ 20 21 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MAX32672_H_ 22 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MAX32672_H_ 23 24 #ifndef TARGET_NUM 25 #define TARGET_NUM 32672 26 #endif 27 28 #define MXC_NUMCORES 1 29 30 #include <stdint.h> 31 32 #ifndef FALSE 33 #define FALSE (0) 34 #endif 35 36 #ifndef TRUE 37 #define TRUE (1) 38 #endif 39 40 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ 41 #if defined(__GNUC__) 42 #ifndef __weak 43 #define __weak __attribute__((weak)) 44 #endif 45 46 #elif defined(__CC_ARM) 47 48 #define inline __inline 49 #pragma anon_unions 50 51 #endif 52 53 typedef enum { 54 NonMaskableInt_IRQn = -14, 55 HardFault_IRQn = -13, 56 MemoryManagement_IRQn = -12, 57 BusFault_IRQn = -11, 58 UsageFault_IRQn = -10, 59 SVCall_IRQn = -5, 60 DebugMonitor_IRQn = -4, 61 PendSV_IRQn = -2, 62 SysTick_IRQn = -1, 63 64 /* Device-specific interrupt sources (external to ARM core) */ 65 /* table entry number */ 66 /* |||| */ 67 /* |||| table offset address */ 68 /* vvvv vvvvvv */ 69 70 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ 71 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ 72 RSV02_IRQn, /* 0x12 0x0048 18: Reserved */ 73 RTC_IRQn, /* 0x13 0x004C 19: RTC */ 74 TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */ 75 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ 76 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ 77 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ 78 TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */ 79 TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 */ 80 TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */ 81 RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */ 82 RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */ 83 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ 84 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ 85 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ 86 SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */ 87 SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */ 88 SPI2_IRQn, /* 0x22 0x0088 34: SPI2 */ 89 RSV19_IRQn, /* 0x23 0x008C 35: Reserved */ 90 ADC_IRQn, /* 0x24 0x0090 36: ADC */ 91 RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ 92 RSV22_IRQn, /* 0x26 0x0098 38: Magstripe DSP */ 93 FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */ 94 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ 95 GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO1 */ 96 RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */ 97 CRYPTO_IRQn, /* 0x2B 0x00AC 43: Crypto */ 98 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ 99 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ 100 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ 101 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ 102 RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */ 103 RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */ 104 UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */ 105 RSV35_IRQn, /* 0x33 0x00CC 51: Contactless Link Control */ 106 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ 107 RSV37_IRQn, /* 0x35 0x00D4 53: Smart Card 1 */ 108 RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */ 109 RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */ 110 RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */ 111 RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */ 112 RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */ 113 RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */ 114 RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */ 115 RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */ 116 RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */ 117 RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ 118 RSV48_IRQn, /* 0x40 0x0100 64: Reserved */ 119 RSV49_IRQn, /* 0x41 0x0104 65: Reserved */ 120 RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ 121 RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ 122 RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ 123 RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ 124 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ 125 RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ 126 RSV56_IRQn, /* 0x48 0x0120 72: Reserved */ 127 WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */ 128 RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */ 129 RSV59_IRQn, /* 0x4B 0x012C 75: Reserved */ 130 RSV60_IRQn, /* 0x4C 0x0130 76: Reserved */ 131 RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ 132 I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */ 133 RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */ 134 RSV64_IRQn, /* 0x50 0x0140 80: Reserved */ 135 RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ 136 RSV66_IRQn, /* 0x52 0x0148 82: Reserved */ 137 RSV67_IRQn, /* 0x53 0x014C 83: One Wire Master */ 138 DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */ 139 DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */ 140 DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */ 141 DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */ 142 DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */ 143 DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */ 144 DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */ 145 DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */ 146 RSV76_IRQn, /* 0x5C 0x0170 92: Reserved */ 147 RSV77_IRQn, /* 0x5D 0x0174 93: Reserved */ 148 RSV78_IRQn, /* 0x5E 0x0178 94: Reserved */ 149 RSV79_IRQn, /* 0x5F 0x017C 95: Reserved */ 150 RSV80_IRQn, /* 0x60 0x0180 96: Reserved */ 151 RSV81_IRQn, /* 0x61 0x0184 97: Reserved */ 152 ECC_IRQn, /* 0x62 0x0188 98: Error Correction */ 153 RSV83_IRQn, /* 0x63 0x018C 99: Reserved */ 154 RSV84_IRQn, /* 0x64 0x0190 100: Reserved */ 155 SCA_IRQn, /* 0x65 0x0194 101: Crypto Accelerator */ 156 RSV86_IRQn, /* 0x66 0x0198 102: Reserved */ 157 FLC1_IRQn, /* 0x67 0x019C 103: Flash Controller 1 */ 158 UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */ 159 RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */ 160 RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */ 161 RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */ 162 RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */ 163 RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */ 164 RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */ 165 RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */ 166 RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */ 167 AES_IRQn, /* 0x71 0x01C4 113: AES */ 168 RSV98_IRQn, /* 0x72 0x01C8 114: Reserved */ 169 I2S_IRQn, /* 0x73 0x01CC 115: Reserved */ 170 RSV100_IRQn, /* 0x74 0x01D0 116: Reserved */ 171 RSV101_IRQn, /* 0x75 0x01D4 117: Reserved */ 172 RSV102_IRQn, /* 0x76 0x01D8 118: Reserved */ 173 RSV103_IRQn, /* 0x77 0x01DC 119: Reserved */ 174 RSV104_IRQn, /* 0x78 0x01E0 120: Reserved */ 175 RSV105_IRQn, /* 0x79 0x01E4 121: Reserved */ 176 QDEC_IRQn, /* 0x7A 0x01E8 122: Quadrature Decoder Interface */ 177 RSV107_IRQn, /* 0x7B 0x01EC 123: Reserved */ 178 MXC_IRQ_EXT_COUNT, 179 } IRQn_Type; 180 181 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) 182 183 /* ================================================================================ */ 184 /* ================ Processor and Core Peripheral Section ================ */ 185 /* ================================================================================ */ 186 187 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ 188 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ 189 #define __MPU_PRESENT 1 /*!< MPU present or not */ 190 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 191 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 192 #define __FPU_PRESENT 1 /*!< FPU present or not */ 193 194 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */ 195 #include "system_max32672.h" /*!< System Header */ 196 197 /* ================================================================================ */ 198 /* ================== Device Specific Memory Section ================== */ 199 /* ================================================================================ */ 200 201 #define MXC_ROM_MEM_BASE 0x00000000UL 202 #define MXC_ROM_MEM_SIZE 0x00020000UL 203 #define MXC_XIP_MEM_BASE 0x08000000UL 204 #define MXC_XIP_MEM_SIZE 0x08000000UL 205 #define MXC_FLASH0_MEM_BASE 0x10000000UL 206 #define MXC_FLASH1_MEM_BASE 0x10080000UL 207 #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE 208 #define MXC_FLASH_PAGE_SIZE 0x00002000UL 209 #define MXC_FLASH_MEM_SIZE 0x00080000UL 210 #define MXC_INFO0_MEM_BASE 0x10800000UL 211 #define MXC_INFO1_MEM_BASE 0x10802000UL 212 #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE 213 #define MXC_INFO_MEM_SIZE 0x00002000UL 214 #define MXC_SRAM_MEM_BASE 0x20000000UL 215 #define MXC_SRAM_MEM_SIZE 0x00032000UL 216 #define MXC_XIP_DATA_MEM_BASE 0x80000000UL 217 #define MXC_XIP_DATA_MEM_SIZE 0x20000000UL 218 219 /* ================================================================================ */ 220 /* ================ Device Specific Peripheral Section ================ */ 221 /* ================================================================================ */ 222 223 /* 224 Base addresses and configuration settings for all MAX32672 peripheral modules. 225 */ 226 227 /******************************************************************************/ 228 /* Global control */ 229 #define MXC_BASE_GCR ((uint32_t)0x40000000UL) 230 #define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR) 231 232 /******************************************************************************/ 233 /* Non-battery backed SI Registers */ 234 #define MXC_BASE_SIR ((uint32_t)0x40000400UL) 235 #define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR) 236 237 /******************************************************************************/ 238 /* Non-battery backed Function Control */ 239 #define MXC_BASE_FCR ((uint32_t)0x40000800UL) 240 #define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR) 241 242 /******************************************************************************/ 243 /* Crypto Toolbox */ 244 #define MXC_BASE_CTB ((uint32_t)0x40001000UL) 245 #define MXC_CTB ((mxc_ctb_regs_t *)MXC_BASE_CTB) 246 247 /******************************************************************************/ 248 /* Trim System Initalization Register */ 249 #define MXC_BASE_TRIMSIR ((uint32_t)0x40105400UL) 250 #define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR) 251 252 // DEPRECATED(10-24-2022): Scheduled for removal. 253 #define MXC_ECC ((mxc_ecc_regs_t *)MXC_BASE_TRIMSIR) 254 255 /******************************************************************************/ 256 /* Watchdog */ 257 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) 258 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) 259 #define MXC_BASE_WDT1 ((uint32_t)0x40003400UL) 260 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) 261 262 /******************************************************************************/ 263 /* System and User AES Keys */ 264 #define MXC_BASE_SYS_AESKEYS ((uint32_t)0x40205000UL) 265 #define MXC_SYS_AESKEYS ((mxc_sys_aeskeys_regs_t *)MXC_BASE_SYS_AESKEYS) 266 267 #define MXC_BASE_USR_AESKEYS ((uint32_t)0x40005000UL) 268 #define MXC_USR_AESKEYS ((mxc_usr_aeskeys_regs_t *)MXC_BASE_USR_AESKEYS) 269 270 /* 271 * @deprecated (1-10-2023): Scheduled for removal. Use MXC_BASE_SYS_AESKEYS instead. 272 */ 273 #define MXC_BASE_AESKEY MXC_BASE_SYS_AESKEYS 274 275 /* 276 * @deprecated (1-10-2023): Scheduled for removal. Use MXC_SYS_AESKEYS instead. 277 */ 278 #define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_SYS_AESKEY) 279 280 /* 281 * @deprecated (4-7-2023): Scheduled for removal. Use MXC_BASE_SYS_AESKEYS instead. 282 */ 283 #define MXC_BASE_AESKEYS MXC_BASE_SYS_AESKEYS 284 285 /* 286 * @deprecated (4-7-2023): Scheduled for removal. Use MXC_SYS_AESKEYS instead. 287 */ 288 #define MXC_AESKEYS MXC_SYS_AESKEYS 289 290 /******************************************************************************/ 291 /* Real Time Clock */ 292 #define MXC_BASE_RTC ((uint32_t)0x40106000UL) 293 #define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC) 294 295 /******************************************************************************/ 296 /* Power Sequencer */ 297 #define MXC_BASE_PWRSEQ ((uint32_t)0x40106800UL) 298 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) 299 300 /******************************************************************************/ 301 /* MISC Control */ 302 #define MXC_BASE_MCR ((uint32_t)0x40106C00UL) 303 #define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR) 304 305 /******************************************************************************/ 306 /* AES */ 307 #define MXC_BASE_AES ((uint32_t)0x40207400UL) 308 #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) 309 310 #define MXC_SYS_AES ((mxc_sys_aes_regs_t *)MXC_BASE_AES) 311 312 /******************************************************************************/ 313 /* GPIO */ 314 #define MXC_CFG_GPIO_INSTANCES (3) 315 #define MXC_CFG_GPIO_PINS_PORT (32) 316 317 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) 318 #define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0) 319 #define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL) 320 #define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1) 321 322 #define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : -1) 323 324 #define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : 0) 325 326 #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (i) == 1 ? GPIO1_IRQn : 0) 327 328 /******************************************************************************/ 329 /* CRC */ 330 #define MXC_BASE_CRC ((uint32_t)0x4000F000UL) 331 #define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC) 332 333 /******************************************************************************/ 334 /* Timer */ 335 #define SEC(s) (((uint32_t)s) * 1000000UL) 336 #define MSEC(ms) (ms * 1000UL) 337 #define USEC(us) (us) 338 339 #define MXC_CFG_TMR_INSTANCES (6) 340 341 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) 342 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) 343 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) 344 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) 345 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) 346 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) 347 #define MXC_BASE_TMR3 ((uint32_t)0x40013000UL) 348 #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) 349 #define MXC_BASE_TMR4 ((uint32_t)0x40114000UL) 350 #define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) 351 #define MXC_BASE_TMR5 ((uint32_t)0x40115000UL) 352 #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) 353 354 #define MXC_TMR_GET_IRQ(i) \ 355 (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ 356 (i) == 1 ? TMR1_IRQn : \ 357 (i) == 2 ? TMR2_IRQn : \ 358 (i) == 3 ? TMR3_IRQn : \ 359 (i) == 4 ? TMR4_IRQn : \ 360 (i) == 5 ? TMR5_IRQn : \ 361 0) 362 363 #define MXC_TMR_GET_BASE(i) \ 364 ((i) == 0 ? MXC_BASE_TMR0 : \ 365 (i) == 1 ? MXC_BASE_TMR1 : \ 366 (i) == 2 ? MXC_BASE_TMR2 : \ 367 (i) == 3 ? MXC_BASE_TMR3 : \ 368 (i) == 4 ? MXC_BASE_TMR4 : \ 369 (i) == 5 ? MXC_BASE_TMR5 : \ 370 0) 371 372 #define MXC_TMR_GET_TMR(i) \ 373 ((i) == 0 ? MXC_TMR0 : \ 374 (i) == 1 ? MXC_TMR1 : \ 375 (i) == 2 ? MXC_TMR2 : \ 376 (i) == 3 ? MXC_TMR3 : \ 377 (i) == 4 ? MXC_TMR4 : \ 378 (i) == 5 ? MXC_TMR5 : \ 379 0) 380 381 #define MXC_TMR_GET_IDX(p) \ 382 ((p) == MXC_TMR0 ? 0 : \ 383 (p) == MXC_TMR1 ? 1 : \ 384 (p) == MXC_TMR2 ? 2 : \ 385 (p) == MXC_TMR3 ? 3 : \ 386 (p) == MXC_TMR4 ? 4 : \ 387 (p) == MXC_TMR5 ? 5 : \ 388 -1) 389 390 /******************************************************************************/ 391 /* I2C */ 392 #define MXC_I2C_INSTANCES (3) 393 #define MXC_I2C_NUM_TARGET_ADDR (4) 394 #define MXC_I2C_FIFO_DEPTH (8) 395 396 #define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) 397 #define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0) 398 #define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) 399 #define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1) 400 #define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL) 401 #define MXC_I2C2 ((mxc_i2c_regs_t *)MXC_BASE_I2C2) 402 403 #define MXC_I2C_GET_IRQ(i) \ 404 (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : (i) == 2 ? I2C2_IRQn : 0) 405 406 #define MXC_I2C_GET_BASE(i) \ 407 ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : (i) == 2 ? MXC_BASE_I2C2 : 0) 408 409 #define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : (i) == 2 ? MXC_I2C2 : 0) 410 411 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : (p) == MXC_I2C2 ? 2 : -1) 412 413 /******************************************************************************/ 414 /* DMA */ 415 #define MXC_DMA_CHANNELS (12) 416 #define MXC_DMA_INSTANCES (1) 417 418 #define MXC_BASE_DMA ((uint32_t)0x40028000UL) 419 #define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA) 420 421 #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) 422 423 #define MXC_DMA_CH_GET_IRQ(i) \ 424 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ 425 ((i) == 1) ? DMA1_IRQn : \ 426 ((i) == 2) ? DMA2_IRQn : \ 427 ((i) == 3) ? DMA3_IRQn : \ 428 ((i) == 4) ? DMA4_IRQn : \ 429 ((i) == 5) ? DMA5_IRQn : \ 430 ((i) == 6) ? DMA6_IRQn : \ 431 ((i) == 7) ? DMA7_IRQn : \ 432 ((i) == 8) ? DMA8_IRQn : \ 433 ((i) == 9) ? DMA9_IRQn : \ 434 ((i) == 10) ? DMA10_IRQn : \ 435 ((i) == 11) ? DMA11_IRQn : \ 436 0)) 437 438 /******************************************************************************/ 439 /* FLC */ 440 #define MXC_FLC_INSTANCES (2) 441 442 #define MXC_BASE_FLC0 ((uint32_t)0x40029000UL) 443 #define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0) 444 #define MXC_BASE_FLC1 ((uint32_t)0x40029400UL) 445 #define MXC_FLC1 ((mxc_flc_regs_t *)MXC_BASE_FLC1) 446 447 #define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : \ 448 (i) == 1 ? FLC1_IRQn 0) 449 450 #define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : (i) == 1 ? MXC_BASE_FLC1 : 0) 451 452 #define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : (i) == 1 ? MXC_FLC1 : 0) 453 454 #define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : (p) == MXC_FLC1 ? 1 : -1) 455 456 /******************************************************************************/ 457 /* Instruction Cache */ 458 #define MXC_BASE_ICC ((uint32_t)0x4002A000UL) 459 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) 460 461 /******************************************************************************/ 462 /* ADC */ 463 #define MXC_BASE_ADC ((uint32_t)0x40034000UL) 464 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) 465 466 /******************************************************************************/ 467 /* One Wire Master */ 468 #define MXC_BASE_OWM ((uint32_t)0x4003D000UL) 469 #define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM) 470 471 /******************************************************************************/ 472 /* UART / Serial Port Interface */ 473 #define MXC_UART_INSTANCES (4) 474 #define MXC_UART_FIFO_DEPTH (8) 475 476 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL) 477 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) 478 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL) 479 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) 480 #define MXC_BASE_UART2 ((uint32_t)0x40044000UL) 481 #define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2) 482 #define MXC_BASE_UART3 ((uint32_t)0x40145000UL) 483 #define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3) 484 485 #define MXC_UART_GET_IRQ(i) \ 486 (IRQn_Type)((i) == 0 ? UART0_IRQn : \ 487 (i) == 1 ? UART1_IRQn : \ 488 (i) == 2 ? UART2_IRQn : \ 489 (i) == 3 ? UART3_IRQn : \ 490 0) 491 492 #define MXC_UART_GET_BASE(i) \ 493 ((i) == 0 ? MXC_BASE_UART0 : \ 494 (i) == 1 ? MXC_BASE_UART1 : \ 495 (i) == 2 ? MXC_BASE_UART2 : \ 496 (i) == 3 ? MXC_BASE_UART3 : \ 497 0) 498 499 #define MXC_UART_GET_UART(i) \ 500 ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : (i) == 3 ? MXC_UART3 : 0) 501 502 #define MXC_UART_GET_IDX(p) \ 503 ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : (p) == MXC_UART3 ? 3 : -1) 504 505 /******************************************************************************/ 506 /* SPI */ 507 #define MXC_SPI_INSTANCES (3) 508 #define MXC_SPI_SS_INSTANCES (4) 509 #define MXC_SPI_FIFO_DEPTH (32) 510 511 #define MXC_BASE_SPI0 ((uint32_t)0x40046000UL) 512 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) 513 #define MXC_BASE_SPI1 ((uint32_t)0x40047000UL) 514 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) 515 #define MXC_BASE_SPI2 ((uint32_t)0x40048000UL) 516 #define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2) 517 518 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI2 ? 2 : -1) 519 520 #define MXC_SPI_GET_BASE(i) \ 521 ((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : (i) == 2 ? MXC_BASE_SPI2 : 0) 522 523 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : (i) == 2 ? MXC_SPI2 : 0) 524 525 #define MXC_SPI_GET_IRQ(i) \ 526 (IRQn_Type)((i) == 0 ? SPI0_IRQn : (i) == 1 ? SPI1_IRQn : (i) == 2 ? SPI2_IRQn : 0) 527 528 /******************************************************************************/ 529 /* TRNG */ 530 #define MXC_BASE_TRNG ((uint32_t)0x4004D000UL) 531 #define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG) 532 533 /******************************************************************************/ 534 #define MXC_BASE_I2S ((uint32_t)0x40060000UL) 535 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) 536 537 /******************************************************************************/ 538 /* Quadrature Decoder Interface */ 539 #define MXC_BASE_QDEC ((uint32_t)0x40063000UL) 540 #define MXC_QDEC ((mxc_qdec_regs_t *)MXC_BASE_QDEC) 541 542 /******************************************************************************/ 543 /* Bit Shifting */ 544 #define MXC_F_BIT_0 (1 << 0) 545 #define MXC_F_BIT_1 (1 << 1) 546 #define MXC_F_BIT_2 (1 << 2) 547 #define MXC_F_BIT_3 (1 << 3) 548 #define MXC_F_BIT_4 (1 << 4) 549 #define MXC_F_BIT_5 (1 << 5) 550 #define MXC_F_BIT_6 (1 << 6) 551 #define MXC_F_BIT_7 (1 << 7) 552 #define MXC_F_BIT_8 (1 << 8) 553 #define MXC_F_BIT_9 (1 << 9) 554 #define MXC_F_BIT_10 (1 << 10) 555 #define MXC_F_BIT_11 (1 << 11) 556 #define MXC_F_BIT_12 (1 << 12) 557 #define MXC_F_BIT_13 (1 << 13) 558 #define MXC_F_BIT_14 (1 << 14) 559 #define MXC_F_BIT_15 (1 << 15) 560 #define MXC_F_BIT_16 (1 << 16) 561 #define MXC_F_BIT_17 (1 << 17) 562 #define MXC_F_BIT_18 (1 << 18) 563 #define MXC_F_BIT_19 (1 << 19) 564 #define MXC_F_BIT_20 (1 << 20) 565 #define MXC_F_BIT_21 (1 << 21) 566 #define MXC_F_BIT_22 (1 << 22) 567 #define MXC_F_BIT_23 (1 << 23) 568 #define MXC_F_BIT_24 (1 << 24) 569 #define MXC_F_BIT_25 (1 << 25) 570 #define MXC_F_BIT_26 (1 << 26) 571 #define MXC_F_BIT_27 (1 << 27) 572 #define MXC_F_BIT_28 (1 << 28) 573 #define MXC_F_BIT_29 (1 << 29) 574 #define MXC_F_BIT_30 (1 << 30) 575 #define MXC_F_BIT_31 (1 << 31) 576 577 /******************************************************************************/ 578 /* Bit Banding */ 579 #define BITBAND(reg, bit) \ 580 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ 581 ((bit) << 2)) 582 583 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) 584 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) 585 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) 586 587 #define MXC_SETFIELD(reg, mask, setting) (reg = ((reg) & ~(mask)) | ((setting) & (mask))) 588 589 /******************************************************************************/ 590 /* SCB CPACR */ 591 592 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ 593 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ 594 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ 595 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ 596 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ 597 598 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MAX32672_H_ 599
