1 /****************************************************************************** 2 * 3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 4 * Analog Devices, Inc.), 5 * Copyright (C) 2023-2024 Analog Devices, Inc. 6 * 7 * Licensed under the Apache License, Version 2.0 (the "License"); 8 * you may not use this file except in compliance with the License. 9 * You may obtain a copy of the License at 10 * 11 * http://www.apache.org/licenses/LICENSE-2.0 12 * 13 * Unless required by applicable law or agreed to in writing, software 14 * distributed under the License is distributed on an "AS IS" BASIS, 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 * See the License for the specific language governing permissions and 17 * limitations under the License. 18 * 19 ******************************************************************************/ 20 21 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_MAX78002_H_ 22 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_MAX78002_H_ 23 24 // clang-format off 25 #ifndef TARGET_NUM 26 #define TARGET_NUM 78002 27 #endif 28 29 #define MXC_NUMCORES 2 30 31 #include <stdint.h> 32 33 #ifndef FALSE 34 #define FALSE (0) 35 #endif 36 37 #ifndef TRUE 38 #define TRUE (1) 39 #endif 40 41 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ 42 #if defined(__GNUC__) 43 #ifndef __weak 44 #define __weak __attribute__((weak)) 45 #endif 46 47 #elif defined(__CC_ARM) 48 49 #define inline __inline 50 #pragma anon_unions 51 52 #endif 53 54 typedef enum { 55 #ifndef __riscv // not RISC-V 56 NonMaskableInt_IRQn = -14, 57 HardFault_IRQn = -13, 58 MemoryManagement_IRQn = -12, 59 BusFault_IRQn = -11, 60 UsageFault_IRQn = -10, 61 SVCall_IRQn = -5, 62 DebugMonitor_IRQn = -4, 63 PendSV_IRQn = -2, 64 SysTick_IRQn = -1, 65 66 /* Device-specific interrupt sources (external to ARM core) */ 67 /* table entry number */ 68 /* |||| */ 69 /* |||| table offset address */ 70 /* vvvv vvvvvv */ 71 72 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ 73 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ 74 USB_IRQn, /* 0x12 0x0048 18: USB */ 75 RTC_IRQn, /* 0x13 0x004C 19: RTC */ 76 TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */ 77 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ 78 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ 79 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ 80 TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */ 81 TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 (LP) */ 82 TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 (LP) */ 83 RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */ 84 RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */ 85 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ 86 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ 87 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ 88 SPI1_IRQn, /* 0x20 0x0080 32: SPI1 */ 89 RSV17_IRQn, /* 0x21 0x0084 33: Reserved */ 90 RSV18_IRQn, /* 0x22 0x0088 34: Reserved */ 91 RSV19_IRQn, /* 0x23 0x008C 35: Reserved */ 92 ADC_IRQn, /* 0x24 0x0090 36: ADC */ 93 RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ 94 RSV22_IRQn, /* 0x26 0x0098 38: Reserved */ 95 FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller */ 96 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ 97 GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO1 */ 98 GPIO2_IRQn, /* 0x2A 0x00A8 42: GPIO2 (LP) */ 99 RSV27_IRQn, /* 0x2B 0x00AC 43: Reserved */ 100 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ 101 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ 102 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ 103 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ 104 RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */ 105 RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */ 106 UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */ 107 RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */ 108 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ 109 RSV37_IRQn, /* 0x35 0x00D4 53: Reserved */ 110 RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */ 111 RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */ 112 RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */ 113 RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */ 114 RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */ 115 RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */ 116 RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */ 117 RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */ 118 RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */ 119 RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ 120 RSV48_IRQn, /* 0x40 0x0100 64: Reserved */ 121 RSV49_IRQn, /* 0x41 0x0104 65: Reserved */ 122 RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ 123 RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ 124 RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ 125 WUT_IRQn, /* 0x45 0x0114 69: Wakeup Timer */ 126 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO and AIN Wakeup */ 127 RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ 128 SPI0_IRQn, /* 0x48 0x0120 72: SPI0 */ 129 WDT1_IRQn, /* 0x49 0x0124 73: LP Watchdog */ 130 RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */ 131 PT_IRQn, /* 0x4B 0x012C 75: Pulse Train */ 132 RSV60_IRQn, /* 0x4C 0x0130 76: Reserved */ 133 RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ 134 I2C2_IRQn, /* 0x4E 0x0138 78: I2C2 */ 135 RISCV_IRQn, /* 0x4F 0x013C 79: RISC-V */ 136 RSV64_IRQn, /* 0x50 0x0140 80: Reserved */ 137 RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ 138 SDHC_IRQn, /* 0x52 0x0148 82: SDHC SDIO */ 139 OWM_IRQn, /* 0x53 0x014C 83: One Wire Master */ 140 RSV68_IRQn, /* 0x54 0x0150 84: Reserved */ 141 RSV69_IRQn, /* 0x55 0x0154 85: Reserved */ 142 RSV70_IRQn, /* 0x56 0x0158 86: Reserved */ 143 RSV71_IRQn, /* 0x57 0x015C 87: Reserved */ 144 RSV72_IRQn, /* 0x58 0x0160 88: Reserved */ 145 RSV73_IRQn, /* 0x59 0x0164 89: Reserved */ 146 RSV74_IRQn, /* 0x5A 0x0168 90: Reserved */ 147 RSV75_IRQn, /* 0x5B 0x016C 91: Reserved */ 148 RSV76_IRQn, /* 0x5C 0x0170 92: Reserved */ 149 RSV77_IRQn, /* 0x5D 0x0174 93: Reserved */ 150 RSV78_IRQn, /* 0x5E 0x0178 94: Reserved */ 151 RSV79_IRQn, /* 0x5F 0x017C 95: Reserved */ 152 USBDMA_IRQn, /* 0x60 0x0180 96: USB DMA */ 153 RSV81_IRQn, /* 0x61 0x0184 97: Reserved */ 154 ECC_IRQn, /* 0x62 0x0188 98: ECC */ 155 DVS_IRQn, /* 0x63 0x018C 99: DVS */ 156 SIMO_IRQn, /* 0x64 0x0190 100: SIMO */ 157 RSV85_IRQn, /* 0x65 0x0194 101: Reserved */ 158 RSV86_IRQn, /* 0x66 0x0198 102: Reserved */ 159 RSV87_IRQn, /* 0x67 0x019C 103: Reserved */ 160 UART3_IRQn, /* 0x68 0x01A0 104: UART 3 (LP) */ 161 RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */ 162 RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */ 163 PCIF_IRQn, /* 0x6B 0x01AC 107: PCIF (Camera) */ 164 RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */ 165 RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */ 166 RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */ 167 RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */ 168 RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */ 169 AES_IRQn, /* 0x71 0x01C4 113: AES */ 170 CRC_IRQn, /* 0x72 0x01C8 114: CRC */ 171 I2S_IRQn, /* 0x73 0x01CC 115: I2S */ 172 CNN_FIFO_IRQn, /* 0x74 0x01D0 116: CNN FIFO */ 173 CNN_IRQn, /* 0x75 0x01D4 117: CNN */ 174 RSV102_IRQn, /* 0x76 0x01D8 118: Reserved */ 175 LPCMP_IRQn, /* 0x77 0x01DC 119: LP Comparator */ 176 CSI2_IRQn, /* 0x78 0x01E0 120: CSI2 APB */ 177 #else // __riscv 178 PF_IRQn = 4, /* 0x04,4 PFW | SYSFAULT | CM4 */ 179 WDT0_IRQn, /* 0x05,5 Watchdog 0 */ 180 GPIOWAKE_IRQn = 6, /* 0x06,6 GPIO Wakeup */ 181 AINComp_IRQn = 6, /* 0x06,6 AINComp */ 182 RTC_IRQn, /* 0x07,7 RTC */ 183 TMR0_IRQn, /* 0x08,8 Timer 0 */ 184 TMR1_IRQn, /* 0x09,9 Timer 1 */ 185 TMR2_IRQn, /* 0x0A,10 Timer 2 */ 186 TMR3_IRQn, /* 0x0B,11 Timer 3 */ 187 TMR4_IRQn, /* 0x0C,12 Timer 4 (LP) */ 188 TMR5_IRQn, /* 0x0D,13 Timer 5 (LP) */ 189 I2C0_IRQn, /* 0x0E,14 I2C0 */ 190 UART0_IRQn, /* 0x0F,15 UART 0 */ 191 RSV16_IRQn, /* 0x10,16 Reserved */ 192 I2C1_IRQn, /* 0x11,17 I2C1 */ 193 UART1_IRQn, /* 0x12,18 UART 1 */ 194 UART2_IRQn, /* 0x13,19 UART 2 */ 195 I2C2_IRQn, /* 0x14,20 I2C2 */ 196 UART3_IRQn, /* 0x15,21 LPUART */ 197 SPI1_IRQn, /* 0x16,22 SPI1 */ 198 WUT_IRQn, /* 0x17,23 WUT */ 199 FLC0_IRQn, /* 0x18,24 Flash Controller */ 200 GPIO0_IRQn, /* 0x19,25 GPIO0 */ 201 GPIO1_IRQn, /* 0x1A,26 GPIO1 */ 202 GPIO2_IRQn, /* 0x1B,27 GPIO2 (LP) */ 203 DMA0_IRQn, /* 0x1C,28 DMA0 */ 204 DMA1_IRQn, /* 0x1D,29 DMA1 */ 205 DMA2_IRQn, /* 0x1E,30 DMA2 */ 206 DMA3_IRQn, /* 0x1F,31 DMA3 */ 207 RSV32_IRQn, /* 0x20,32 Reserved */ 208 RSV33_IRQn, /* 0x21,33 Reserved */ 209 RSV34_IRQn, /* 0x22,34 Reserved */ 210 RSV35_IRQn, /* 0x23,35 Reserved */ 211 RSV36_IRQn, /* 0x24,36 Reserved */ 212 RSV37_IRQn, /* 0x25,37 Reserved */ 213 RSV38_IRQn, /* 0x26,38 Reserved */ 214 RSV39_IRQn, /* 0x27,39 Reserved */ 215 RSV40_IRQn, /* 0x28,40 Reserved */ 216 RSV41_IRQn, /* 0x29,41 Reserved */ 217 RSV42_IRQn, /* 0x2A,42 Reserved */ 218 RSV43_IRQn, /* 0x2B,43 Reserved */ 219 RSV44_IRQn, /* 0x2C,44 Reserved */ 220 RSV45_IRQn, /* 0x2D,45 Reserved */ 221 AES_IRQn, /* 0x2E,46 AES */ 222 TRNG_IRQn, /* 0x2F,47 True Random Number Generator */ 223 WDT1_IRQn, /* 0x30,48 Watchdog 1 (LP) */ 224 DVS_IRQn, /* 0x31,49 DVS Controller */ 225 SIMO_IRQn, /* 0x32,50 SIMO Controller */ 226 CRC_IRQn, /* 0x33,51 CRC */ 227 PT_IRQn, /* 0x34,52 Pulse train */ 228 ADC_IRQn, /* 0x35,53 ADC */ 229 OWM_IRQn, /* 0x36,54 One Wire Master */ 230 I2S_IRQn, /* 0x37,55 I2S */ 231 CNN_FIFO_IRQn, /* 0x38,56 CNN FIFO */ 232 CNN_IRQn, /* 0x39,57 CNN */ 233 RSV58_IRQn, /* 0x3A,58 Reserved */ 234 PCIF_IRQn, /* 0x3B,59 Parallel Camera IF */ 235 #endif // __riscv 236 MXC_IRQ_EXT_COUNT, 237 } IRQn_Type; 238 239 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) 240 241 /* ================================================================================ */ 242 /* ================ Processor and Core Peripheral Section ================ */ 243 /* ================================================================================ */ 244 245 #ifndef __riscv 246 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ 247 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ 248 #define __MPU_PRESENT 1 /*!< MPU present or not */ 249 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 250 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 251 #define __FPU_PRESENT 1 /*!< FPU present or not */ 252 253 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */ 254 255 #else // __riscv 256 257 #include <core_rv32.h> 258 259 #endif // __riscv 260 261 #include "system_max78002.h" /*!< System Header */ 262 263 /* ================================================================================ */ 264 /* ================== Device Specific Memory Section ================== */ 265 /* ================================================================================ */ 266 267 #define MXC_ROM_MEM_BASE 0x00000000UL 268 #define MXC_ROM_MEM_SIZE 0x00010000UL 269 #define MXC_FLASH0_MEM_BASE 0x10000000UL 270 #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE 271 #define MXC_FLASH_PAGE_SIZE 0x00004000UL 272 #define MXC_FLASH_MEM_SIZE 0x00280000UL 273 #define MXC_INFO0_MEM_BASE 0x10800000UL 274 #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE 275 #define MXC_INFO_MEM_SIZE 0x00008000UL 276 #define MXC_SRAM_MEM_BASE 0x20000000UL 277 #define MXC_SRAM_MEM_SIZE 0x00060000UL 278 279 /* ================================================================================ */ 280 /* ================ Device Specific Peripheral Section ================ */ 281 /* ================================================================================ */ 282 283 /* 284 Base addresses and configuration settings for all MAX78002 peripheral modules. 285 */ 286 287 /******************************************************************************/ 288 /* Global control */ 289 #define MXC_BASE_GCR ((uint32_t)0x40000000UL) 290 #define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR) 291 292 /******************************************************************************/ 293 /* Non-battery backed SI Registers */ 294 #define MXC_BASE_SIR ((uint32_t)0x40000400UL) 295 #define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR) 296 297 /******************************************************************************/ 298 /* Non-Battery Backed Function Control */ 299 #define MXC_BASE_FCR ((uint32_t)0x40000800UL) 300 #define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR) 301 302 /******************************************************************************/ 303 /* Windowed Watchdog Timer */ 304 #define MXC_CFG_WDT_INSTANCES (2) 305 306 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) 307 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) 308 #define MXC_BASE_WDT1 ((uint32_t)0x40080800UL) 309 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) 310 311 /******************************************************************************/ 312 /* SIMO Control */ 313 #define MXC_BASE_SIMO ((uint32_t)0x40004400UL) 314 #define MXC_SIMO ((mxc_simo_regs_t *)MXC_BASE_SIMO) 315 316 /******************************************************************************/ 317 /* Dynamic Voltage Scaling (DVS) Control */ 318 #define MXC_BASE_DVS ((uint32_t)0x40004800UL) 319 #define MXC_DVS ((mxc_dvs_regs_t *)MXC_BASE_DVS) 320 321 /******************************************************************************/ 322 /* Trim System Initalization Register */ 323 #define MXC_BASE_TRIMSIR ((uint32_t)0x40005400UL) 324 #define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR) 325 326 /******************************************************************************/ 327 /* GCFR */ 328 #define MXC_BASE_GCFR ((uint32_t)0x40005800UL) 329 #define MXC_GCFR ((mxc_gcfr_regs_t *)MXC_BASE_GCFR) 330 331 /******************************************************************************/ 332 /* Real Time Clock */ 333 #define MXC_BASE_RTC ((uint32_t)0x40006000UL) 334 #define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC) 335 336 /******************************************************************************/ 337 /* Wake-Up Timer (WUT) */ 338 #define MXC_BASE_WUT ((uint32_t)0x40006400UL) 339 #define MXC_WUT ((mxc_wut_regs_t *)MXC_BASE_WUT) 340 341 /******************************************************************************/ 342 /* Power Sequencer */ 343 #define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) 344 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) 345 346 /******************************************************************************/ 347 /* Misc Control */ 348 #define MXC_BASE_MCR ((uint32_t)0x40006C00UL) 349 #define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR) 350 351 /******************************************************************************/ 352 /* AES */ 353 #define MXC_BASE_AES ((uint32_t)0x40007400UL) 354 #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) 355 356 /******************************************************************************/ 357 /* AES Keys */ 358 #define MXC_BASE_AESKEYS ((uint32_t)0x40007800UL) 359 #define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS) 360 361 // DEPRECATED(1-10-2023): Scheduled for removal. 362 #define MXC_BASE_AESKEY MXC_BASE_AESKEYS 363 #define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_AESKEY) 364 365 /******************************************************************************/ 366 /* GPIO */ 367 #define MXC_CFG_GPIO_INSTANCES (4) 368 #define MXC_CFG_GPIO_PINS_PORT (32) 369 370 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) 371 #define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0) 372 #define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL) 373 #define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1) 374 #define MXC_BASE_GPIO2 ((uint32_t)0x40080400UL) 375 #define MXC_GPIO2 ((mxc_gpio_regs_t *)MXC_BASE_GPIO2) 376 //GPIO3 dummy address it does not live here and will be handled in code different than other gpios but this allow our macros to work. 377 #define MXC_BASE_GPIO3 ((uint32_t)0x4000B000UL) 378 #define MXC_GPIO3 ((mxc_gpio_regs_t *)MXC_BASE_GPIO3) 379 380 #define MXC_GPIO_GET_IDX(p) \ 381 ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : (p) == MXC_GPIO2 ? 2 : (p) == MXC_GPIO3 ? 3 : -1) 382 383 #define MXC_GPIO_GET_GPIO(i) \ 384 ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : (i) == 2 ? MXC_GPIO2 : (i) == 3 ? MXC_GPIO3 : 0) 385 386 #define MXC_GPIO_GET_IRQ(i) \ 387 ((i) == 0 ? GPIO0_IRQn : \ 388 (i) == 1 ? GPIO1_IRQn : \ 389 (i) == 2 ? GPIO2_IRQn : \ 390 (i) == 3 ? GPIOWAKE_IRQn : \ 391 0) 392 393 /******************************************************************************/ 394 /* Parallel Camera Interface */ 395 #define MXC_BASE_PCIF ((uint32_t)0x4000E000UL) 396 #define MXC_PCIF ((mxc_cameraif_regs_t *)MXC_BASE_PCIF) 397 398 /******************************************************************************/ 399 /* CRC */ 400 #define MXC_BASE_CRC ((uint32_t)0x4000F000UL) 401 #define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC) 402 403 /******************************************************************************/ 404 /* Timer */ 405 #define SEC(s) (((uint32_t)s) * 1000000UL) 406 #define MSEC(ms) (ms * 1000UL) 407 #define USEC(us) (us) 408 409 #define MXC_CFG_TMR_INSTANCES (6) 410 411 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) 412 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) 413 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) 414 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) 415 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) 416 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) 417 #define MXC_BASE_TMR3 ((uint32_t)0x40013000UL) 418 #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) 419 #define MXC_BASE_TMR4 ((uint32_t)0x40080C00UL) 420 #define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) 421 #define MXC_BASE_TMR5 ((uint32_t)0x40081000UL) 422 #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) 423 424 #define MXC_TMR_GET_IRQ(i) \ 425 (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ 426 (i) == 1 ? TMR1_IRQn : \ 427 (i) == 2 ? TMR2_IRQn : \ 428 (i) == 3 ? TMR3_IRQn : \ 429 (i) == 4 ? TMR4_IRQn : \ 430 (i) == 5 ? TMR5_IRQn : \ 431 0) 432 433 #define MXC_TMR_GET_BASE(i) \ 434 ((i) == 0 ? MXC_BASE_TMR0 : \ 435 (i) == 1 ? MXC_BASE_TMR1 : \ 436 (i) == 2 ? MXC_BASE_TMR2 : \ 437 (i) == 3 ? MXC_BASE_TMR3 : \ 438 (i) == 4 ? MXC_BASE_TMR4 : \ 439 (i) == 5 ? MXC_BASE_TMR5 : \ 440 0) 441 442 #define MXC_TMR_GET_TMR(i) \ 443 ((i) == 0 ? MXC_TMR0 : \ 444 (i) == 1 ? MXC_TMR1 : \ 445 (i) == 2 ? MXC_TMR2 : \ 446 (i) == 3 ? MXC_TMR3 : \ 447 (i) == 4 ? MXC_TMR4 : \ 448 (i) == 5 ? MXC_TMR5 : \ 449 0) 450 451 #define MXC_TMR_GET_IDX(p) \ 452 ((p) == MXC_TMR0 ? 0 : \ 453 (p) == MXC_TMR1 ? 1 : \ 454 (p) == MXC_TMR2 ? 2 : \ 455 (p) == MXC_TMR3 ? 3 : \ 456 (p) == MXC_TMR4 ? 4 : \ 457 (p) == MXC_TMR5 ? 5 : \ 458 -1) 459 460 /******************************************************************************/ 461 /* I2C */ 462 #define MXC_I2C_INSTANCES (3) 463 464 #define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) 465 #define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0) 466 #define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) 467 #define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1) 468 #define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL) 469 #define MXC_I2C2 ((mxc_i2c_regs_t *)MXC_BASE_I2C2) 470 471 #define MXC_I2C_GET_IRQ(i) \ 472 (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : (i) == 2 ? I2C2_IRQn : 0) 473 474 #define MXC_I2C_GET_BASE(i) \ 475 ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : (i) == 2 ? MXC_BASE_I2C2 : 0) 476 477 #define MXC_I2C_GET_TMR(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : (i) == 2 ? MXC_I2C2 : 0) 478 479 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : (p) == MXC_I2C2 ? 2 : -1) 480 #define MXC_I2C_FIFO_DEPTH (8) 481 482 /******************************************************************************/ 483 /* DMA */ 484 #define MXC_DMA_CHANNELS (4) 485 #define MXC_DMA_INSTANCES (1) 486 487 #define MXC_BASE_DMA ((uint32_t)0x40028000UL) 488 #define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA) 489 490 #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) 491 492 #define MXC_DMA_CH_GET_IRQ(i) ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : ((i) == 1) ? DMA1_IRQn : \ 493 ((i) == 2) ? DMA2_IRQn : ((i) == 3) ? DMA3_IRQn : 0)) 494 495 /******************************************************************************/ 496 /* FLC */ 497 #define MXC_FLC_INSTANCES (1) 498 499 #define MXC_BASE_FLC0 ((uint32_t)0x40029000UL) 500 #define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0) 501 #define MXC_FLC MXC_FLC0 502 503 #define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : 0) 504 505 #define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : 0) 506 507 #define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : 0) 508 509 #define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : -1) 510 511 /******************************************************************************/ 512 /* Instruction Cache */ 513 #define MXC_ICC_INSTANCES (2) 514 515 #define MXC_BASE_ICC0 ((uint32_t)0x4002A000UL) 516 #define MXC_ICC0 ((mxc_icc_regs_t *)MXC_BASE_ICC0) 517 518 #define MXC_BASE_ICC1 ((uint32_t)0x4002A800UL) 519 #define MXC_ICC1 ((mxc_icc_regs_t *)MXC_BASE_ICC1) 520 521 #define MXC_ICC MXC_ICC0 522 // ICC1 is the RISC-V cache 523 524 /******************************************************************************/ 525 /* ADC */ 526 #define MXC_BASE_ADC ((uint32_t)0x40034000UL) 527 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) 528 #define MXC_ADC_MAX_CLOCK 8000000 // Maximum ADC clock in Hz 529 530 /*******************************************************************************/ 531 /* Pulse Train Generation */ 532 #define MXC_CFG_PT_INSTANCES (4) 533 534 #define MXC_BASE_PTG ((uint32_t)0x4003C000UL) 535 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) 536 #define MXC_BASE_PT0 ((uint32_t)0x4003C020UL) 537 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) 538 #define MXC_BASE_PT1 ((uint32_t)0x4003C040UL) 539 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) 540 #define MXC_BASE_PT2 ((uint32_t)0x4003C060UL) 541 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) 542 #define MXC_BASE_PT3 ((uint32_t)0x4003C080UL) 543 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) 544 545 #define MXC_PT_GET_BASE(i) \ 546 ((i) == 0 ? MXC_BASE_PT0 : \ 547 (i) == 1 ? MXC_BASE_PT1 : \ 548 (i) == 2 ? MXC_BASE_PT2 : \ 549 (i) == 3 ? MXC_BASE_PT3 : \ 550 0) 551 552 #define MXC_PT_GET_PT(i) \ 553 ((i) == 0 ? MXC_PT0 : (i) == 1 ? MXC_PT1 : (i) == 2 ? MXC_PT2 : (i) == 3 ? MXC_PT3 : 0) 554 555 #define MXC_PT_GET_IDX(p) \ 556 ((p) == MXC_PT0 ? 0 : (p) == MXC_PT1 ? 1 : (p) == MXC_PT2 ? 2 : (p) == MXC_PT3 ? 3 : -1) 557 558 /******************************************************************************/ 559 /* One Wire Master */ 560 #define MXC_BASE_OWM ((uint32_t)0x4003D000UL) 561 #define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM) 562 563 /******************************************************************************/ 564 /* Semaphore */ 565 #define MXC_CFG_SEMA_INSTANCES (8) 566 567 #define MXC_BASE_SEMA ((uint32_t)0x4003E000UL) 568 #define MXC_SEMA ((mxc_sema_regs_t *)MXC_BASE_SEMA) 569 570 /******************************************************************************/ 571 /* UART / Serial Port Interface */ 572 #define MXC_UART_INSTANCES (4) 573 #define MXC_UART_FIFO_DEPTH (8) 574 575 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL) 576 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) 577 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL) 578 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) 579 #define MXC_BASE_UART2 ((uint32_t)0x40044000UL) 580 #define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2) 581 #define MXC_BASE_UART3 ((uint32_t)0x40081400UL) 582 #define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3) 583 584 #define MXC_UART_GET_IRQ(i) \ 585 (IRQn_Type)((i) == 0 ? UART0_IRQn : \ 586 (i) == 1 ? UART1_IRQn : \ 587 (i) == 2 ? UART2_IRQn : \ 588 (i) == 3 ? UART3_IRQn : \ 589 0) 590 591 #define MXC_UART_GET_BASE(i) \ 592 ((i) == 0 ? MXC_BASE_UART0 : \ 593 (i) == 1 ? MXC_BASE_UART1 : \ 594 (i) == 2 ? MXC_BASE_UART2 : \ 595 (i) == 3 ? MXC_BASE_UART3 : \ 596 0) 597 598 #define MXC_UART_GET_UART(i) \ 599 ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : (i) == 3 ? MXC_UART3 : 0) 600 601 #define MXC_UART_GET_IDX(p) \ 602 ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : (p) == MXC_UART3 ? 3 : -1) 603 604 /******************************************************************************/ 605 /* SPI */ 606 #ifndef __riscv 607 #define MXC_SPI_INSTANCES (2) 608 #else 609 #define MXC_SPI_INSTANCES (1) 610 #endif // __riscv 611 #define MXC_SPI_SS_INSTANCES (4) 612 #define MXC_SPI_FIFO_DEPTH (32) 613 614 #define MXC_BASE_SPI1 ((uint32_t)0x40046000UL) 615 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) 616 #define MXC_SPI1_TS_INSTANCES (1) 617 #ifndef __riscv 618 #define MXC_BASE_SPI0 ((uint32_t)0x400BE000UL) 619 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) 620 #define MXC_SPI0_TS_INSTANCES (3) 621 622 // Note: These must be in order SPI1, SPI0 to support RISC-V 623 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI1 ? 0 : (p) == MXC_SPI0 ? 1 : -1) 624 625 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI1 : (i) == 1 ? MXC_BASE_SPI0 : 0) 626 627 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI1 : (i) == 1 ? MXC_SPI0 : 0) 628 629 #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI1_IRQn : (i) == 1 ? SPI0_IRQn : 0) 630 631 #define MXC_SPI_GET_TOTAL_TS(p) \ 632 ((p) == MXC_SPI1 ? MXC_SPI1_TS_INSTANCES : (p) == MXC_SPI0 ? MXC_SPI0_TS_INSTANCES : 0) 633 #else // __riscv 634 635 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI1 ? 0 : -1) 636 637 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI1 : 0) 638 639 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI1 : 0) 640 641 #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI1_IRQn : 0) 642 643 #define MXC_SPI_GET_TOTAL_TS(p) ((p) == MXC_SPI1 ? MXC_SPI1_TS_INSTANCES : 0) 644 645 #endif // __riscv 646 647 /******************************************************************************/ 648 /* TRNG */ 649 #define MXC_BASE_TRNG ((uint32_t)0x4004D000UL) 650 #define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG) 651 652 /******************************************************************************/ 653 /* I2S */ 654 #define MXC_BASE_I2S ((uint32_t)0x40060000UL) 655 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) 656 657 /******************************************************************************/ 658 /* CSI2 */ 659 #define MXC_BASE_CSI2 ((uint32_t)0x40062000UL) 660 #define MXC_CSI2 ((mxc_csi2_regs_t *)MXC_BASE_CSI2) 661 662 /******************************************************************************/ 663 /* Low Power General control */ 664 #define MXC_BASE_LPGCR ((uint32_t)0x40080000UL) 665 #define MXC_LPGCR ((mxc_lpgcr_regs_t *)MXC_BASE_LPGCR) 666 667 /******************************************************************************/ 668 /* Low-Power Comparator */ 669 #define MXC_BASE_LPCMP ((uint32_t)0x40088000UL) 670 #define MXC_LPCMP ((mxc_lpcmp_regs_t *)MXC_BASE_LPCMP) 671 672 /******************************************************************************/ 673 /* USB */ 674 #define MXC_BASE_USBHS ((uint32_t)0x400B1000UL) 675 #define MXC_USBHS ((mxc_usbhs_regs_t *)MXC_BASE_USBHS) 676 #define MXC_USBHS_NUM_EP 12 /* HW must have at least EP 0 CONTROL + 11 IN/OUT */ 677 #define MXC_USBHS_NUM_DMA 8 /* HW must have at least this many DMA channels */ 678 #define MXC_USBHS_MAX_PACKET 512 679 680 /******************************************************************************/ 681 /* SDHC */ 682 #define MXC_BASE_SDHC ((uint32_t)0x400B6000UL) 683 #define MXC_SDHC ((mxc_sdhc_regs_t *)MXC_BASE_SDHC) 684 685 /******************************************************************************/ 686 /* CSI2 FIFO */ 687 #define MXC_BASE_CSI2_FIFO ((uint32_t)0x400C0800UL) 688 #define MXC_CSI2_FIFO ((uint32_t *)MXC_BASE_CSI2_FIFO) 689 #define MXC_CSI2_FIFO_DEPTH (128) 690 691 /******************************************************************************/ 692 /* CNN FIFO */ 693 #define MXC_BASE_CNN_FIFO ((uint32_t)0x400C0400UL) 694 #define MXC_CNN_FIFO ((mxc_cnn_fifo_regs_t *)MXC_BASE_CNN_FIFO) 695 696 /******************************************************************************/ 697 /* CNN */ 698 #define MXC_BASE_CNN ((uint32_t)0x50000000UL) 699 #define MXC_CNN ((mxc_cnn_regs_t *)MXC_BASE_CNN) 700 701 /******************************************************************************/ 702 /* Bit Shifting */ 703 #define MXC_F_BIT_0 (1 << 0) 704 #define MXC_F_BIT_1 (1 << 1) 705 #define MXC_F_BIT_2 (1 << 2) 706 #define MXC_F_BIT_3 (1 << 3) 707 #define MXC_F_BIT_4 (1 << 4) 708 #define MXC_F_BIT_5 (1 << 5) 709 #define MXC_F_BIT_6 (1 << 6) 710 #define MXC_F_BIT_7 (1 << 7) 711 #define MXC_F_BIT_8 (1 << 8) 712 #define MXC_F_BIT_9 (1 << 9) 713 #define MXC_F_BIT_10 (1 << 10) 714 #define MXC_F_BIT_11 (1 << 11) 715 #define MXC_F_BIT_12 (1 << 12) 716 #define MXC_F_BIT_13 (1 << 13) 717 #define MXC_F_BIT_14 (1 << 14) 718 #define MXC_F_BIT_15 (1 << 15) 719 #define MXC_F_BIT_16 (1 << 16) 720 #define MXC_F_BIT_17 (1 << 17) 721 #define MXC_F_BIT_18 (1 << 18) 722 #define MXC_F_BIT_19 (1 << 19) 723 #define MXC_F_BIT_20 (1 << 20) 724 #define MXC_F_BIT_21 (1 << 21) 725 #define MXC_F_BIT_22 (1 << 22) 726 #define MXC_F_BIT_23 (1 << 23) 727 #define MXC_F_BIT_24 (1 << 24) 728 #define MXC_F_BIT_25 (1 << 25) 729 #define MXC_F_BIT_26 (1 << 26) 730 #define MXC_F_BIT_27 (1 << 27) 731 #define MXC_F_BIT_28 (1 << 28) 732 #define MXC_F_BIT_29 (1 << 29) 733 #define MXC_F_BIT_30 (1 << 30) 734 #define MXC_F_BIT_31 (1 << 31) 735 736 /******************************************************************************/ 737 /* Bit Banding */ 738 #define BITBAND(reg, bit) \ 739 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ 740 ((bit) << 2)) 741 742 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) 743 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) 744 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) 745 746 #define MXC_SETFIELD(reg, mask, setting) (reg = ((reg) & ~(mask)) | ((setting) & (mask))) 747 748 /******************************************************************************/ 749 /* SCB CPACR */ 750 751 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ 752 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ 753 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ 754 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ 755 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ 756 757 // clang-format on 758 759 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_MAX78002_H_ 760
