1 /** 2 * @file max32662.h 3 * @brief Device-specific perhiperal header file 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_MAX32662_H_ 27 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_MAX32662_H_ 28 29 #ifndef TARGET_NUM 30 #define TARGET_NUM 32662 31 #endif 32 33 #include <stdint.h> 34 35 #ifndef FALSE 36 #define FALSE (0) 37 #endif 38 39 #ifndef TRUE 40 #define TRUE (1) 41 #endif 42 43 #if !defined(__GNUC__) 44 #define CMSIS_VECTAB_VIRTUAL 45 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h" 46 #endif /* !__GNUC__ */ 47 48 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ 49 #if defined(__GNUC__) /* GCC */ 50 #ifndef __weak 51 #define __weak __attribute__((weak)) 52 #endif 53 54 #elif defined(__CC_ARM) /* Keil */ 55 56 #define inline __inline 57 #pragma anon_unions 58 59 #endif 60 61 typedef enum { 62 NonMaskableInt_IRQn = -14, 63 HardFault_IRQn = -13, 64 MemoryManagement_IRQn = -12, 65 BusFault_IRQn = -11, 66 UsageFault_IRQn = -10, 67 SVCall_IRQn = -5, 68 DebugMonitor_IRQn = -4, 69 PendSV_IRQn = -2, 70 SysTick_IRQn = -1, 71 72 /* Device-specific interrupt sources (external to ARM core) */ 73 /* table entry number */ 74 /* |||| */ 75 /* |||| table offset address */ 76 /* vvvv vvvvvv */ 77 78 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ 79 WDT_IRQn, /* 0x11 0x0044 17: Watchdog */ 80 RSV2_IRQn, /* 0x12 0x0048 18: Reserved */ 81 RTC_IRQn, /* 0x13 0x004C 19: RTC */ 82 TRNG_IRQn, /* 0x14 0x0050 20: TRNG */ 83 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ 84 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ 85 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ 86 TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */ 87 RSV9_IRQn, /* 0x19 0x0064 25: Reserved */ 88 RSV10_IRQn, /* 0x1A 0x0068 26: Reserved */ 89 RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */ 90 RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */ 91 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ 92 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ 93 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ 94 SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */ 95 SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */ 96 RSV18_IRQn, /* 0x22 0x0088 34: Reserved */ 97 RSV19_IRQn, /* 0x23 0x008C 35: Reserved */ 98 ADC_IRQn, /* 0x24 0x0090 36: ADC */ 99 RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ 100 RSV22_IRQn, /* 0x26 0x0098 38: Reserved */ 101 FLC_IRQn, /* 0x27 0x009C 39: Flash Controller */ 102 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ 103 RSV25_IRQn, /* 0x29 0x00A4 41: Reserved */ 104 RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */ 105 RSV27_IRQn, /* 0x2B 0x00AC 43: Reserved */ 106 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ 107 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ 108 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ 109 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ 110 RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */ 111 RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */ 112 RSV34_IRQn, /* 0x32 0x00C8 50: Reserved */ 113 RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */ 114 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ 115 RSV37_IRQn, /* 0x35 0x00D4 53: Reserved */ 116 RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */ 117 RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */ 118 RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */ 119 RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */ 120 RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */ 121 RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */ 122 RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */ 123 RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */ 124 RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */ 125 RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ 126 RSV48_IRQn, /* 0x40 0x0100 64: Reserved */ 127 RSV49_IRQn, /* 0x41 0x0104 65: Reserved */ 128 RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ 129 RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ 130 RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ 131 RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ 132 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ 133 RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ 134 RSV56_IRQn, /* 0x48 0x0120 72: Reserved */ 135 RSV57_IRQn, /* 0x49 0x0124 73: Reserved */ 136 RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */ 137 PT_IRQn, /* 0x4B 0x012C 75: Pulse Train */ 138 RSV60_IRQn, /* 0x4C 0x0130 76: Reserved */ 139 RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ 140 RSV62_IRQn, /* 0x4E 0x0138 78: Reserved */ 141 RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */ 142 RSV64_IRQn, /* 0x50 0x0140 80: Reserved */ 143 RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ 144 RSV66_IRQn, /* 0x52 0x0148 82: Reserved */ 145 RSV67_IRQn, /* 0x53 0x014C 83: Reserved */ 146 RSV68_IRQn, /* 0x54 0x0150 84: Reserved */ 147 RSV69_IRQn, /* 0x55 0x0154 85: Reserved */ 148 RSV70_IRQn, /* 0x56 0x0158 86: Reserved */ 149 RSV71_IRQn, /* 0x57 0x015C 87: Reserved */ 150 RSV72_IRQn, /* 0x58 0x0160 88: Reserved */ 151 RSV73_IRQn, /* 0x59 0x0164 89: Reserved */ 152 RSV74_IRQn, /* 0x5A 0x0168 90: Reserved */ 153 RSV75_IRQn, /* 0x5B 0x016C 91: Reserved */ 154 RSV76_IRQn, /* 0x5C 0x0170 92: Reserved */ 155 RSV77_IRQn, /* 0x5D 0x0174 93: Reserved */ 156 RSV78_IRQn, /* 0x5E 0x0178 94: Reserved */ 157 RSV79_IRQn, /* 0x5F 0x017C 95: Reserved */ 158 RSV80_IRQn, /* 0x60 0x0180 96: Reserved */ 159 RSV81_IRQn, /* 0x61 0x0184 97: Reserved */ 160 ECC_IRQn, /* 0x62 0x0188 98: Reserved */ 161 RSV83_IRQn, /* 0x63 0x018C 99: Reserved */ 162 RSV84_IRQn, /* 0x64 0x0190 100: Reserved */ 163 RSV85_IRQn, /* 0x65 0x0194 101: Reserved */ 164 RSV86_IRQn, /* 0x66 0x0198 102: Reserved */ 165 RSV87_IRQn, /* 0x67 0x019C 103: Reserved */ 166 RSV88_IRQn, /* 0x68 0x01A0 104: Reserved */ 167 RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */ 168 RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */ 169 RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */ 170 RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */ 171 RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */ 172 RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */ 173 RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */ 174 RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */ 175 AES_IRQn, /* 0x71 0x01C4 113: AES */ 176 RSV98_IRQn, /* 0x72 0x01C8 114: Reserved */ 177 I2S_IRQn, /* 0x73 0x01CC 115: I2S */ 178 RSV100_IRQn, /* 0x74 0x01D0 116: Reserved */ 179 RSV101_IRQn, /* 0x75 0x01D4 117: Reserved */ 180 RSV102_IRQn, /* 0x76 0x01D8 118: Reserved */ 181 RSV103_IRQn, /* 0x77 0x01DC 119: Reserved */ 182 RSV104_IRQn, /* 0x78 0x01E0 120: Reserved */ 183 RSV105_IRQn, /* 0x79 0x01E4 121: Reserved */ 184 RSV106_IRQn, /* 0x7A 0x01E8 122: Reserved */ 185 CAN_IRQn, /* 0x7B 0x01EC 123: CAN */ 186 MXC_IRQ_EXT_COUNT, 187 } IRQn_Type; 188 189 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) 190 191 /* ================================================================================ */ 192 /* ================ Processor and Core Peripheral Section ================ */ 193 /* ================================================================================ */ 194 195 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ 196 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ 197 #define __MPU_PRESENT 1 /*!< MPU present or not */ 198 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 199 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 200 #define __FPU_PRESENT 1 /*!< FPU present or not */ 201 202 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */ 203 #include "system_max32662.h" /*!< System Header */ 204 205 /* ================================================================================ */ 206 /* ================== Device Specific Memory Section ================== */ 207 /* ================================================================================ */ 208 209 #define MXC_ROM_MEM_BASE 0x00000000UL 210 #define MXC_ROM_MEM_SIZE 0x00020000UL 211 #define MXC_FLASH_MEM_BASE 0x10000000UL 212 #define MXC_FLASH_PAGE_SIZE 0x00002000UL 213 #define MXC_FLASH_MEM_SIZE 0x00040000UL 214 #define MXC_INFO0_MEM_BASE 0x10800000UL 215 #define MXC_INFO1_MEM_BASE 0x10802000UL 216 #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE 217 #define MXC_INFO_MEM_SIZE 0x00002000UL 218 #define MXC_INFO0_MEM_SIZE 0x00002000UL 219 #define MXC_INFO1_MEM_SIZE 0x00002000UL 220 #define MXC_SRAM_MEM_BASE 0x20000000UL 221 #define MXC_SRAM_MEM_SIZE 0x00014000UL 222 223 /* ================================================================================ */ 224 /* ================ Device Specific Peripheral Section ================ */ 225 /* ================================================================================ */ 226 227 /* 228 Base addresses and configuration settings for all MAX32662 peripheral modules. 229 */ 230 231 /******************************************************************************/ 232 /* Global Control */ 233 #define MXC_BASE_GCR ((uint32_t)0x40000000UL) 234 #define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR) 235 236 /******************************************************************************/ 237 /* Non-battery backed SI Registers */ 238 #define MXC_BASE_SIR ((uint32_t)0x40000400UL) 239 #define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR) 240 241 /******************************************************************************/ 242 /* Function Control Registers */ 243 #define MXC_BASE_FCR ((uint32_t)0x40000800UL) 244 #define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR) 245 246 /******************************************************************************/ 247 /* Watchdog */ 248 #define MXC_BASE_WDT ((uint32_t)0x40003000UL) 249 #define MXC_WDT ((mxc_wdt_regs_t *)MXC_BASE_WDT) 250 #define MXC_WDT0 MXC_WDT 251 252 /******************************************************************************/ 253 /* AES Keys */ 254 #define MXC_BASE_AESKEYS ((uint32_t)0x40205000UL) 255 #define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS) 256 257 // DEPRECATED(1-10-2023): Scheduled for removal. 258 #define MXC_BASE_AESKEY MXC_BASE_AESKEYS 259 #define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_AESKEY) 260 261 /******************************************************************************/ 262 /* Trim System Initalization Register */ 263 #define MXC_BASE_TRIMSIR ((uint32_t)0x40105400UL) 264 #define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR) 265 266 /******************************************************************************/ 267 /* Real Time Clock */ 268 #define MXC_BASE_RTC ((uint32_t)0x40106000UL) 269 #define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC) 270 271 /******************************************************************************/ 272 /* Power Sequencer */ 273 #define MXC_BASE_PWRSEQ ((uint32_t)0x40106800UL) 274 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) 275 276 /******************************************************************************/ 277 /* Misc Control */ 278 #define MXC_BASE_MCR ((uint32_t)0x40106C00UL) 279 #define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR) 280 281 /******************************************************************************/ 282 /* AES */ 283 #define MXC_BASE_AES ((uint32_t)0x40207400UL) 284 #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) 285 286 /******************************************************************************/ 287 /* GPIO */ 288 #define MXC_CFG_GPIO_INSTANCES (1) 289 #define MXC_CFG_GPIO_PINS_PORT (32) 290 291 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) 292 #define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0) 293 294 #define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : -1) 295 296 #define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0) 297 298 #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0) 299 300 /******************************************************************************/ 301 /* Timer */ 302 #define SEC(s) (((uint32_t)s) * 1000000UL) 303 #define MSEC(ms) (ms * 1000UL) 304 #define USEC(us) (us) 305 306 #define MXC_CFG_TMR_INSTANCES (4) 307 308 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) 309 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) 310 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) 311 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) 312 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) 313 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) 314 #define MXC_BASE_TMR3 ((uint32_t)0x40113000UL) 315 #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) 316 317 #define MXC_TMR_GET_IRQ(i) \ 318 (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ 319 (i) == 1 ? TMR1_IRQn : \ 320 (i) == 2 ? TMR2_IRQn : \ 321 (i) == 3 ? TMR3_IRQn : \ 322 0) 323 324 #define MXC_TMR_GET_BASE(i) \ 325 ((i) == 0 ? MXC_BASE_TMR0 : \ 326 (i) == 1 ? MXC_BASE_TMR1 : \ 327 (i) == 2 ? MXC_BASE_TMR2 : \ 328 (i) == 3 ? MXC_BASE_TMR3 : \ 329 0) 330 331 #define MXC_TMR_GET_TMR(i) \ 332 ((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : (i) == 3 ? MXC_TMR3 : 0) 333 334 #define MXC_TMR_GET_IDX(p) \ 335 ((p) == MXC_TMR0 ? 0 : (p) == MXC_TMR1 ? 1 : (p) == MXC_TMR2 ? 2 : (p) == MXC_TMR3 ? 3 : -1) 336 337 /******************************************************************************/ 338 /* I2C */ 339 #define MXC_I2C_INSTANCES (2) 340 #define MXC_I2C_FIFO_DEPTH (8) 341 342 #define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) 343 #define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0) 344 #define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) 345 #define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1) 346 347 #define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : 0) 348 349 #define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : 0) 350 351 #define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : 0) 352 353 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : -1) 354 355 /******************************************************************************/ 356 /* DMA */ 357 #define MXC_DMA_CHANNELS (4) 358 #define MXC_DMA_INSTANCES (1) 359 360 #define MXC_BASE_DMA ((uint32_t)0x40028000UL) 361 #define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA) 362 363 #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) 364 365 #define MXC_DMA_CH_GET_IRQ(i) \ 366 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ 367 ((i) == 1) ? DMA1_IRQn : \ 368 ((i) == 2) ? DMA2_IRQn : \ 369 ((i) == 3) ? DMA3_IRQn : \ 370 0)) 371 372 /******************************************************************************/ 373 /* FLC */ 374 #define MXC_FLC_INSTANCES (1) 375 376 #define MXC_BASE_FLC ((uint32_t)0x40029000UL) 377 #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) 378 #define MXC_FLC0 MXC_FLC 379 380 #define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC_IRQn : 0) 381 382 #define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC : 0) 383 384 #define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0) 385 386 #define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC ? 0 : -1) 387 388 /******************************************************************************/ 389 /* Internal Cache Controller */ 390 #define MXC_BASE_ICC ((uint32_t)0x4002A000UL) 391 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) 392 #define MXC_ICC0 MXC_ICC 393 394 /******************************************************************************/ 395 /* ADC */ 396 #define MXC_BASE_ADC ((uint32_t)0x40034000UL) 397 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) 398 #define MXC_ADC_MAX_CLOCK 8000000 // Maximum ADC clock in Hz 399 400 /*******************************************************************************/ 401 /* Pulse Train Generation */ 402 #define MXC_CFG_PT_INSTANCES (4) 403 404 #define MXC_BASE_PTG ((uint32_t)0x4003C000UL) 405 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) 406 #define MXC_BASE_PT0 ((uint32_t)0x4003C020UL) 407 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) 408 #define MXC_BASE_PT1 ((uint32_t)0x4003C040UL) 409 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) 410 #define MXC_BASE_PT2 ((uint32_t)0x4003C060UL) 411 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) 412 #define MXC_BASE_PT3 ((uint32_t)0x4003C080UL) 413 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) 414 415 #define MXC_PT_GET_BASE(i) \ 416 ((i) == 0 ? MXC_BASE_PT0 : \ 417 (i) == 1 ? MXC_BASE_PT1 : \ 418 (i) == 2 ? MXC_BASE_PT2 : \ 419 (i) == 3 ? MXC_BASE_PT3 : \ 420 0) 421 422 #define MXC_PT_GET_PT(i) \ 423 ((i) == 0 ? MXC_PT0 : (i) == 1 ? MXC_PT1 : (i) == 2 ? MXC_PT2 : (i) == 3 ? MXC_PT3 : 0) 424 425 #define MXC_PT_GET_IDX(p) \ 426 ((p) == MXC_PT0 ? 0 : (p) == MXC_PT1 ? 1 : (p) == MXC_PT2 ? 2 : (p) == MXC_PT3 ? 3 : -1) 427 428 /******************************************************************************/ 429 /* UART / Serial Port Interface */ 430 #define MXC_UART_INSTANCES (2) 431 #define MXC_UART_FIFO_DEPTH (8) 432 433 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL) 434 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) 435 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL) 436 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) 437 438 #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : (i) == 1 ? UART1_IRQn : 0) 439 440 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : (i) == 1 ? MXC_BASE_UART1 : 0) 441 442 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : 0) 443 444 #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : -1) 445 446 /******************************************************************************/ 447 /* SPI */ 448 #define MXC_SPI_INSTANCES (2) 449 #define MXC_SPI_SS_INSTANCES (1) 450 #define MXC_SPI_FIFO_DEPTH (32) 451 452 #define MXC_BASE_SPI0 ((uint32_t)0x40046000UL) 453 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) 454 #define MXC_BASE_SPI1 ((uint32_t)0x40047000UL) 455 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) 456 457 #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI0_IRQn : (i) == 1 ? SPI1_IRQn : 0) 458 459 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : 0) 460 461 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : 0) 462 463 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : -1) 464 465 /******************************************************************************/ 466 /* TRNG */ 467 #define MXC_BASE_TRNG ((uint32_t)0x4004D000UL) 468 #define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG) 469 470 /******************************************************************************/ 471 /* I2S */ 472 #define MXC_BASE_I2S ((uint32_t)0x40060000UL) 473 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) 474 475 /******************************************************************************/ 476 /* CAN */ 477 #define MXC_CAN_INSTANCES (1) 478 479 #define MXC_BASE_CAN ((uint32_t)0x40064000UL) 480 #define MXC_CAN ((mxc_can_regs_t *)MXC_BASE_CAN) 481 #define MXC_CAN0 MXC_CAN 482 483 #define MXC_CAN_GET_IDX(p) ((p) == MXC_CAN ? 0 : -1) 484 485 #define MXC_CAN_GET_BASE(i) ((i) == 0 ? MXC_BASE_CAN : 0) 486 487 #define MXC_CAN_GET_CAN(i) ((i) == 0 ? MXC_CAN : 0) 488 489 #define MXC_CAN_GET_IRQ(i) (IRQn_Type)((i) == 0 ? CAN_IRQn : 0) 490 491 /******************************************************************************/ 492 /* Bit Shifting */ 493 #define MXC_F_BIT_0 (1 << 0) 494 #define MXC_F_BIT_1 (1 << 1) 495 #define MXC_F_BIT_2 (1 << 2) 496 #define MXC_F_BIT_3 (1 << 3) 497 #define MXC_F_BIT_4 (1 << 4) 498 #define MXC_F_BIT_5 (1 << 5) 499 #define MXC_F_BIT_6 (1 << 6) 500 #define MXC_F_BIT_7 (1 << 7) 501 #define MXC_F_BIT_8 (1 << 8) 502 #define MXC_F_BIT_9 (1 << 9) 503 #define MXC_F_BIT_10 (1 << 10) 504 #define MXC_F_BIT_11 (1 << 11) 505 #define MXC_F_BIT_12 (1 << 12) 506 #define MXC_F_BIT_13 (1 << 13) 507 #define MXC_F_BIT_14 (1 << 14) 508 #define MXC_F_BIT_15 (1 << 15) 509 #define MXC_F_BIT_16 (1 << 16) 510 #define MXC_F_BIT_17 (1 << 17) 511 #define MXC_F_BIT_18 (1 << 18) 512 #define MXC_F_BIT_19 (1 << 19) 513 #define MXC_F_BIT_20 (1 << 20) 514 #define MXC_F_BIT_21 (1 << 21) 515 #define MXC_F_BIT_22 (1 << 22) 516 #define MXC_F_BIT_23 (1 << 23) 517 #define MXC_F_BIT_24 (1 << 24) 518 #define MXC_F_BIT_25 (1 << 25) 519 #define MXC_F_BIT_26 (1 << 26) 520 #define MXC_F_BIT_27 (1 << 27) 521 #define MXC_F_BIT_28 (1 << 28) 522 #define MXC_F_BIT_29 (1 << 29) 523 #define MXC_F_BIT_30 (1 << 30) 524 #define MXC_F_BIT_31 (1 << 31) 525 526 /******************************************************************************/ 527 /* Bit Banding */ 528 #define BITBAND(reg, bit) \ 529 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ 530 ((bit) << 2)) 531 532 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) 533 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) 534 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) 535 536 #define MXC_SETFIELD(reg, mask, value) ((reg) = ((reg) & ~(mask)) | ((value) & (mask))) 537 538 /******************************************************************************/ 539 /* SCB CPACR */ 540 541 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ 542 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ 543 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ 544 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ 545 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ 546 547 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_MAX32662_H_ 548
