1 /****************************************************************************** 2 * 3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 4 * Analog Devices, Inc.), 5 * Copyright (C) 2023-2024 Analog Devices, Inc. 6 * 7 * Licensed under the Apache License, Version 2.0 (the "License"); 8 * you may not use this file except in compliance with the License. 9 * You may obtain a copy of the License at 10 * 11 * http://www.apache.org/licenses/LICENSE-2.0 12 * 13 * Unless required by applicable law or agreed to in writing, software 14 * distributed under the License is distributed on an "AS IS" BASIS, 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 * See the License for the specific language governing permissions and 17 * limitations under the License. 18 * 19 ******************************************************************************/ 20 21 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_MAX32655_H_ 22 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_MAX32655_H_ 23 24 #ifndef TARGET_NUM 25 #define TARGET_NUM 32655 26 #endif 27 28 #define MXC_NUMCORES 1 29 30 #include <stdint.h> 31 32 #ifndef FALSE 33 #define FALSE (0) 34 #endif 35 36 #ifndef TRUE 37 #define TRUE (1) 38 #endif 39 40 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ 41 #if defined(__GNUC__) 42 #ifndef __weak 43 #define __weak __attribute__((weak)) 44 #endif 45 46 #elif defined(__CC_ARM) 47 48 #define inline __inline 49 #pragma anon_unions 50 51 #endif 52 53 typedef enum { 54 #ifndef __riscv // not RISC-V 55 NonMaskableInt_IRQn = -14, 56 HardFault_IRQn = -13, 57 MemoryManagement_IRQn = -12, 58 BusFault_IRQn = -11, 59 UsageFault_IRQn = -10, 60 SVCall_IRQn = -5, 61 DebugMonitor_IRQn = -4, 62 PendSV_IRQn = -2, 63 SysTick_IRQn = -1, 64 65 /* Device-specific interrupt sources (external to ARM core) */ 66 /* table entry number */ 67 /* |||| */ 68 /* |||| table offset address */ 69 /* vvvv vvvvvv */ 70 71 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ 72 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ 73 RSV02_IRQn, /* 0x12 0x0048 18: Reserved */ 74 RTC_IRQn, /* 0x13 0x004C 19: RTC */ 75 TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */ 76 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ 77 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ 78 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ 79 TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */ 80 TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 (LP) */ 81 TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 (LP) */ 82 RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */ 83 RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */ 84 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ 85 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ 86 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ 87 SPI1_IRQn, /* 0x20 0x0080 32: SPI1 */ 88 RSV17_IRQn, /* 0x21 0x0084 33: Reserved */ 89 RSV18_IRQn, /* 0x22 0x0088 34: Reserved */ 90 RSV19_IRQn, /* 0x23 0x008C 35: Reserved */ 91 ADC_IRQn, /* 0x24 0x0090 36: ADC */ 92 RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ 93 RSV22_IRQn, /* 0x26 0x0098 38: Reserved */ 94 FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller */ 95 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ 96 GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO1 */ 97 GPIO2_IRQn, /* 0x2A 0x00A8 42: GPIO2 (LP) */ 98 RSV27_IRQn, /* 0x2B 0x00AC 43: Reserved */ 99 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ 100 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ 101 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ 102 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ 103 RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */ 104 RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */ 105 UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */ 106 RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */ 107 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ 108 RSV37_IRQn, /* 0x35 0x00D4 53: Reserved */ 109 RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */ 110 BTLE_TX_DONE_IRQn, /* 0x37 0x00DC 55: BTLE TX Done */ 111 BTLE_RX_RCVD_IRQn, /* 0x38 0x00E0 56: BTLE RX Received */ 112 BTLE_RX_ENG_DET_IRQn, /* 0x39 0x00E4 57: BTLE RX Energy Detected */ 113 BTLE_SFD_DET_IRQn, /* 0x3A 0x00E8 58: BTLE SFD Detected */ 114 BTLE_SFD_TO_IRQn, /* 0x3B 0x00EC 59: BTLE SFD Timeout*/ 115 BTLE_GP_EVENT_IRQn, /* 0x3C 0x00F0 60: BTLE Timestamp*/ 116 BTLE_CFO_IRQn, /* 0x3D 0x00F4 61: BTLE CFO Done */ 117 BTLE_SIG_DET_IRQn, /* 0x3E 0x00F8 62: BTLE Signal Detected */ 118 BTLE_AGC_EVENT_IRQn, /* 0x3F 0x00FC 63: BTLE AGC Event */ 119 BTLE_RFFE_SPIM_IRQn, /* 0x40 0x0100 64: BTLE RFFE SPIM Done */ 120 BTLE_TX_AES_IRQn, /* 0x41 0x0104 65: BTLE TX AES Done */ 121 BTLE_RX_AES_IRQn, /* 0x42 0x0108 66: BTLE RX AES Done */ 122 BTLE_INV_APB_ADDR_IRQn, /* 0x43 0x010C 67: BTLE Invalid APB Address*/ 123 BTLE_IQ_DATA_VALID_IRQn, /* 0x44 0x0110 68: BTLE IQ Data Valid */ 124 WUT0_IRQn, /* 0x45 0x0114 69: Wakeup Timer 0 */ 125 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO and AIN Wakeup */ 126 RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ 127 SPI0_IRQn, /* 0x48 0x0120 72: SPI0 */ 128 WDT1_IRQn, /* 0x49 0x0124 73: LP Watchdog */ 129 RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */ 130 PT_IRQn, /* 0x4B 0x012C 75: Pulse Train */ 131 RSV60_IRQn, /* 0x4C 0x0130 76: Reserved */ 132 RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ 133 I2C2_IRQn, /* 0x4E 0x0138 78: I2C2 */ 134 RISCV_IRQn, /* 0x4F 0x013C 79: RISC-V */ 135 RSV64_IRQn, /* 0x50 0x0140 80: Reserved */ 136 RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ 137 RSV66_IRQn, /* 0x52 0x0148 82: Reserved */ 138 OWM_IRQn, /* 0x53 0x014C 83: One Wire Master */ 139 RSV68_IRQn, /* 0x54 0x0150 84: Reserved */ 140 RSV69_IRQn, /* 0x55 0x0154 85: Reserved */ 141 RSV70_IRQn, /* 0x56 0x0158 86: Reserved */ 142 RSV71_IRQn, /* 0x57 0x015C 87: Reserved */ 143 RSV72_IRQn, /* 0x58 0x0160 88: Reserved */ 144 RSV73_IRQn, /* 0x59 0x0164 89: Reserved */ 145 RSV74_IRQn, /* 0x5A 0x0168 90: Reserved */ 146 RSV75_IRQn, /* 0x5B 0x016C 91: Reserved */ 147 RSV76_IRQn, /* 0x5C 0x0170 92: Reserved */ 148 RSV77_IRQn, /* 0x5D 0x0174 93: Reserved */ 149 RSV78_IRQn, /* 0x5E 0x0178 94: Reserved */ 150 RSV79_IRQn, /* 0x5F 0x017C 95: Reserved */ 151 RSV80_IRQn, /* 0x60 0x0180 96: Reserved */ 152 RSV81_IRQn, /* 0x61 0x0184 97: Reserved */ 153 ECC_IRQn, /* 0x62 0x0188 98: ECC */ 154 DVS_IRQn, /* 0x63 0x018C 99: DVS */ 155 SIMO_IRQn, /* 0x64 0x0190 100: SIMO */ 156 RSV85_IRQn, /* 0x65 0x0194 101: Reserved */ 157 RSV86_IRQn, /* 0x66 0x0198 102: Reserved */ 158 RSV87_IRQn, /* 0x67 0x019C 103: Reserved */ 159 UART3_IRQn, /* 0x68 0x01A0 104: UART 3 (LP) */ 160 RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */ 161 RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */ 162 PCIF_IRQn, /* 0x6B 0x01AC 107: PCIF (Camera) */ 163 RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */ 164 RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */ 165 RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */ 166 RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */ 167 RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */ 168 AES_IRQn, /* 0x71 0x01C4 113: AES */ 169 RSV98_IRQn, /* 0x72 0x01C8 114: Reserved */ 170 I2S_IRQn, /* 0x73 0x01CC 115: I2S */ 171 CNN_FIFO_IRQn, /* 0x74 0x01D0 116: CNN FIFO */ 172 CNN_IRQn, /* 0x75 0x01D4 117: CNN */ 173 RSV102_IRQn, /* 0x76 0x01D8 118: Reserved */ 174 LPCMP_IRQn, /* 0x77 0x01Dc 119: LP Comparator */ 175 RSV120_IRQn, /* 0x78 0x01E0 120: Reserved */ 176 RSV121_IRQn, /* 0x79 0x01E4 121: Reserved */ 177 RSV122_IRQn, /* 0x7A 0x01E8 122: Reserved */ 178 RSV123_IRQn, /* 0x7B 0x01EC 123: Reserved */ 179 RSV124_IRQn, /* 0x7C 0x01F0 124: Reserved */ 180 WUT1_IRQn, /* 0x7D 0x01F4 125: ERFO Ready/WUT 1 */ 181 #else // __riscv 182 PF_IRQn = 4, /* 0x04,4 PFW | SYSFAULT | CM4 */ 183 WDT0_IRQn, /* 0x05,5 Watchdog 0 */ 184 GPIOWAKE_IRQn = 6, /* 0x06,6 GPIO Wakeup */ 185 AINComp_IRQn = 6, /* 0x06,6 AINComp */ 186 RTC_IRQn, /* 0x07,7 RTC */ 187 TMR0_IRQn, /* 0x08,8 Timer 0 */ 188 TMR1_IRQn, /* 0x09,9 Timer 1 */ 189 TMR2_IRQn, /* 0x0A,10 Timer 2 */ 190 TMR3_IRQn, /* 0x0B,11 Timer 3 */ 191 TMR4_IRQn, /* 0x0C,12 Timer 4 (LP) */ 192 TMR5_IRQn, /* 0x0D,13 Timer 5 (LP) */ 193 I2C0_IRQn, /* 0x0E,14 I2C0 */ 194 UART0_IRQn, /* 0x0F,15 UART 0 */ 195 CM4_IRQn, /* 0x10,16 CM4 */ 196 I2C1_IRQn, /* 0x11,17 I2C1 */ 197 UART1_IRQn, /* 0x12,18 UART 1 */ 198 UART2_IRQn, /* 0x13,19 UART 2 */ 199 I2C2_IRQn, /* 0x14,20 I2C2 */ 200 UART3_IRQn, /* 0x15,21 LPUART */ 201 SPI1_IRQn, /* 0x16,22 SPI1 */ 202 WUT0_IRQn, /* 0x17,23 WUT0 */ 203 FLC0_IRQn, /* 0x18,24 Flash Controller */ 204 GPIO0_IRQn, /* 0x19,25 GPIO0 */ 205 GPIO1_IRQn, /* 0x1A,26 GPIO1 */ 206 GPIO2_IRQn, /* 0x1B,27 GPIO2 (LP) */ 207 DMA0_IRQn, /* 0x1C,28 DMA0 */ 208 DMA1_IRQn, /* 0x1D,29 DMA1 */ 209 DMA2_IRQn, /* 0x1E,30 DMA2 */ 210 DMA3_IRQn, /* 0x1F,31 DMA3 */ 211 BTLE_TX_DONE_IRQn, /* 0x20,32 Reserved */ 212 BTLE_RX_RCVD_IRQn, /* 0x21,33 Reserved */ 213 BTLE_RX_ENG_DET_IRQn, /* 0x22,34 Reserved */ 214 BTLE_SFD_DET_IRQn, /* 0x23,35 Reserved */ 215 BTLE_SFD_TO_IRQn, /* 0x24,36 Reserved */ 216 BTLE_GP_EVENT_IRQn, /* 0x25,37 Reserved */ 217 BTLE_CFO_IRQn, /* 0x26,38 Reserved */ 218 BTLE_SIG_DET_IRQn, /* 0x27,39 Reserved */ 219 BTLE_AGC_EVENT_IRQn, /* 0x28,40 Reserved */ 220 BTLE_RFFE_SPIM_IRQn, /* 0x29,41 Reserved */ 221 BTLE_TX_AES_IRQn, /* 0x2A,42 Reserved */ 222 BTLE_RX_AES_IRQn, /* 0x2B,43 Reserved */ 223 BTLE_INV_APB_ADDR_IRQn, /* 0x2C,44 Reserved */ 224 BTLE_IQ_DATA_VALID_IRQn, /* 0x2D,45 Reserved */ 225 AES_IRQn, /* 0x2E,46 AES */ 226 TRNG_IRQn, /* 0x2F,47 True Random Number Generator */ 227 WDT1_IRQn, /* 0x30,48 Watchdog 1 (LP) */ 228 DVS_IRQn, /* 0x31,49 DVS Controller */ 229 SIMO_IRQn, /* 0x32,50 SIMO Controller */ 230 WUT1_IRQn, /* 0x33,51 ERFO Ready/WUT1 */ 231 PT_IRQn, /* 0x34,52 Pulse train */ 232 ADC_IRQn, /* 0x35,53 ADC */ 233 OWM_IRQn, /* 0x36,54 One Wire Master */ 234 I2S_IRQn, /* 0x37,55 I2S */ 235 CNN_FIFO_IRQn, /* 0x38,56 CNN FIFO */ 236 CNN_IRQn, /* 0x39,57 CNN */ 237 RSV58_IRQn, /* 0x3A,58 Reserved */ 238 PCIF_IRQn, /* 0x3B,59 Parallel Camera IF */ 239 #endif // __riscv 240 MXC_IRQ_EXT_COUNT, 241 } IRQn_Type; 242 243 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) 244 245 /* ================================================================================ */ 246 /* ================ Processor and Core Peripheral Section ================ */ 247 /* ================================================================================ */ 248 249 #ifndef __riscv 250 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ 251 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ 252 #define __MPU_PRESENT 1 /*!< MPU present or not */ 253 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 254 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 255 #define __FPU_PRESENT 1 /*!< FPU present or not */ 256 257 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */ 258 259 #else // __riscv 260 261 #include <core_rv32.h> 262 263 #endif // __riscv 264 265 #include "system_max32655.h" /*!< System Header */ 266 267 /* ================================================================================ */ 268 /* ================== Device Specific Memory Section ================== */ 269 /* ================================================================================ */ 270 271 #define MXC_ROM_MEM_BASE 0x00000000UL 272 #define MXC_ROM_MEM_SIZE 0x00020000UL 273 #define MXC_FLASH0_MEM_BASE 0x10000000UL 274 #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE 275 #define MXC_FLASH_PAGE_SIZE 0x00002000UL 276 #define MXC_FLASH_MEM_SIZE 0x00080000UL 277 #define MXC_INFO0_MEM_BASE 0x10800000UL 278 #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE 279 #define MXC_INFO_MEM_SIZE 0x00004000UL 280 #define MXC_SRAM_MEM_BASE 0x20000000UL 281 #define MXC_SRAM_MEM_SIZE 0x00020000UL 282 283 /* ================================================================================ */ 284 /* ================ Device Specific Peripheral Section ================ */ 285 /* ================================================================================ */ 286 287 /* 288 Base addresses and configuration settings for all MAX78000 peripheral modules. 289 */ 290 291 /******************************************************************************/ 292 /* Global control */ 293 #define MXC_BASE_GCR ((uint32_t)0x40000000UL) 294 #define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR) 295 296 /******************************************************************************/ 297 /* Non-battery backed SI Registers */ 298 #define MXC_BASE_SIR ((uint32_t)0x40000400UL) 299 #define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR) 300 301 /******************************************************************************/ 302 /* Non-Battery Backed Function Control */ 303 #define MXC_BASE_FCR ((uint32_t)0x40000800UL) 304 #define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR) 305 306 /******************************************************************************/ 307 /* Windowed Watchdog Timer */ 308 #define MXC_CFG_WDT_INSTANCES (2) 309 310 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) 311 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) 312 #define MXC_BASE_WDT1 ((uint32_t)0x40080800UL) 313 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) 314 315 /******************************************************************************/ 316 /* Dynamic Voltage Scaling (DVS) Control */ 317 #define MXC_BASE_DVS ((uint32_t)0x40003C00UL) 318 #define MXC_DVS ((mxc_dvs_regs_t *)MXC_BASE_DVS) 319 320 /******************************************************************************/ 321 /* SIMO Control */ 322 #define MXC_BASE_SIMO ((uint32_t)0x40004400UL) 323 #define MXC_SIMO ((mxc_simo_regs_t *)MXC_BASE_SIMO) 324 325 /******************************************************************************/ 326 /* Trim System Initalization Register */ 327 #define MXC_BASE_TRIMSIR ((uint32_t)0x40005400UL) 328 #define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR) 329 330 /******************************************************************************/ 331 /* Real Time Clock */ 332 #define MXC_BASE_RTC ((uint32_t)0x40006000UL) 333 #define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC) 334 335 /******************************************************************************/ 336 /* Wake-Up Timer (WUT) */ 337 #define MXC_CFG_WUT_INSTANCES (2) 338 339 #define MXC_BASE_WUT0 ((uint32_t)0x40006400UL) 340 #define MXC_WUT0 ((mxc_wut_regs_t *)MXC_BASE_WUT0) 341 #define MXC_WUT MXC_WUT0 342 #define MXC_BASE_WUT1 ((uint32_t)0x40006600UL) 343 #define MXC_WUT1 ((mxc_wut_regs_t *)MXC_BASE_WUT1) 344 345 // Included for legacy compatability after changing WUT_IRQn -> WUT0_IRQn 346 // in system startup files. 347 #define WUT_IRQn WUT0_IRQn 348 #define WUT_IRQHandler WUT0_IRQHandler 349 350 /******************************************************************************/ 351 /* Power Sequencer */ 352 #define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) 353 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) 354 355 /******************************************************************************/ 356 /* Misc Control */ 357 #define MXC_BASE_MCR ((uint32_t)0x40006C00UL) 358 #define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR) 359 360 /******************************************************************************/ 361 /* AES */ 362 #define MXC_BASE_AES ((uint32_t)0x40007400UL) 363 #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) 364 365 /******************************************************************************/ 366 /* AES Keys */ 367 #define MXC_BASE_AESKEYS ((uint32_t)0x40007800UL) 368 #define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS) 369 370 // DEPRECATED(1-10-2023): Scheduled for removal. 371 #define MXC_BASE_AESKEY MXC_BASE_AESKEYS 372 #define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_AESKEY) 373 374 /******************************************************************************/ 375 /* GPIO */ 376 #define MXC_CFG_GPIO_INSTANCES (4) 377 #define MXC_CFG_GPIO_PINS_PORT (32) 378 379 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) 380 #define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0) 381 #define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL) 382 #define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1) 383 #define MXC_BASE_GPIO2 ((uint32_t)0x40080400UL) 384 #define MXC_GPIO2 ((mxc_gpio_regs_t *)MXC_BASE_GPIO2) 385 #define MXC_BASE_GPIO3 ((uint32_t)0x40080600UL) 386 #define MXC_GPIO3 ((mxc_gpio_regs_t *)MXC_BASE_GPIO3) 387 388 #define MXC_GPIO_GET_IDX(p) \ 389 ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : (p) == MXC_GPIO2 ? 2 : (p) == MXC_GPIO3 ? 3 : -1) 390 391 #define MXC_GPIO_GET_GPIO(i) \ 392 ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : (i) == 2 ? MXC_GPIO2 : (i) == 3 ? MXC_GPIO3 : 0) 393 394 #define MXC_GPIO_GET_IRQ(i) \ 395 ((i) == 0 ? GPIO0_IRQn : \ 396 (i) == 1 ? GPIO1_IRQn : \ 397 (i) == 2 ? GPIO2_IRQn : \ 398 (i) == 3 ? GPIOWAKE_IRQn : \ 399 0) 400 401 /******************************************************************************/ 402 /* Parallel Camera Interface */ 403 #define MXC_BASE_PCIF ((uint32_t)0x4000E000UL) 404 #define MXC_PCIF ((mxc_cameraif_regs_t *)MXC_BASE_PCIF) 405 406 /******************************************************************************/ 407 /* CRC */ 408 #define MXC_BASE_CRC ((uint32_t)0x4000F000UL) 409 #define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC) 410 411 /******************************************************************************/ 412 /* Timer */ 413 #define SEC(s) (((uint32_t)s) * 1000000UL) 414 #define MSEC(ms) (ms * 1000UL) 415 #define USEC(us) (us) 416 417 #define MXC_CFG_TMR_INSTANCES (6) 418 419 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) 420 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) 421 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) 422 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) 423 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) 424 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) 425 #define MXC_BASE_TMR3 ((uint32_t)0x40013000UL) 426 #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) 427 #define MXC_BASE_TMR4 ((uint32_t)0x40080C00UL) 428 #define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) 429 #define MXC_BASE_TMR5 ((uint32_t)0x40081000UL) 430 #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) 431 432 #define MXC_TMR_GET_IRQ(i) \ 433 (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ 434 (i) == 1 ? TMR1_IRQn : \ 435 (i) == 2 ? TMR2_IRQn : \ 436 (i) == 3 ? TMR3_IRQn : \ 437 (i) == 4 ? TMR4_IRQn : \ 438 (i) == 5 ? TMR5_IRQn : \ 439 0) 440 441 #define MXC_TMR_GET_BASE(i) \ 442 ((i) == 0 ? MXC_BASE_TMR0 : \ 443 (i) == 1 ? MXC_BASE_TMR1 : \ 444 (i) == 2 ? MXC_BASE_TMR2 : \ 445 (i) == 3 ? MXC_BASE_TMR3 : \ 446 (i) == 4 ? MXC_BASE_TMR4 : \ 447 (i) == 5 ? MXC_BASE_TMR5 : \ 448 0) 449 450 #define MXC_TMR_GET_TMR(i) \ 451 ((i) == 0 ? MXC_TMR0 : \ 452 (i) == 1 ? MXC_TMR1 : \ 453 (i) == 2 ? MXC_TMR2 : \ 454 (i) == 3 ? MXC_TMR3 : \ 455 (i) == 4 ? MXC_TMR4 : \ 456 (i) == 5 ? MXC_TMR5 : \ 457 0) 458 459 #define MXC_TMR_GET_IDX(p) \ 460 ((p) == MXC_TMR0 ? 0 : \ 461 (p) == MXC_TMR1 ? 1 : \ 462 (p) == MXC_TMR2 ? 2 : \ 463 (p) == MXC_TMR3 ? 3 : \ 464 (p) == MXC_TMR4 ? 4 : \ 465 (p) == MXC_TMR5 ? 5 : \ 466 -1) 467 468 /******************************************************************************/ 469 /* I2C */ 470 #define MXC_I2C_INSTANCES (3) 471 472 #define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) 473 #define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0) 474 #define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) 475 #define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1) 476 #define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL) 477 #define MXC_I2C2 ((mxc_i2c_regs_t *)MXC_BASE_I2C2) 478 479 #define MXC_I2C_GET_IRQ(i) \ 480 (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : (i) == 2 ? I2C2_IRQn : 0) 481 482 #define MXC_I2C_GET_BASE(i) \ 483 ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : (i) == 2 ? MXC_BASE_I2C2 : 0) 484 485 #define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : (i) == 2 ? MXC_I2C2 : 0) 486 487 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : (p) == MXC_I2C2 ? 2 : -1) 488 #define MXC_I2C_FIFO_DEPTH (8) 489 490 /******************************************************************************/ 491 /* DMA */ 492 #define MXC_DMA_CHANNELS (4) 493 #define MXC_DMA_INSTANCES (1) 494 495 #define MXC_BASE_DMA ((uint32_t)0x40028000UL) 496 #define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA) 497 498 #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) 499 500 #define MXC_DMA_CH_GET_IRQ(i) \ 501 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ 502 ((i) == 1) ? DMA1_IRQn : \ 503 ((i) == 2) ? DMA2_IRQn : \ 504 ((i) == 3) ? DMA3_IRQn : \ 505 0)) 506 507 /******************************************************************************/ 508 /* FLC */ 509 #define MXC_FLC_INSTANCES (1) 510 511 #define MXC_BASE_FLC0 ((uint32_t)0x40029000UL) 512 #define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0) 513 #define MXC_FLC MXC_FLC0 514 515 #define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : 0) 516 517 #define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : 0) 518 519 #define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : 0) 520 521 #define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : -1) 522 523 /******************************************************************************/ 524 /* Instruction Cache */ 525 #define MXC_ICC_INSTANCES (2) 526 527 #define MXC_BASE_ICC0 ((uint32_t)0x4002A000UL) 528 #define MXC_ICC0 ((mxc_icc_regs_t *)MXC_BASE_ICC0) 529 530 #define MXC_BASE_ICC1 ((uint32_t)0x4002A800UL) 531 #define MXC_ICC1 ((mxc_icc_regs_t *)MXC_BASE_ICC1) 532 533 #define MXC_ICC MXC_ICC0 534 // ICC1 is the RISC-V cache 535 536 /******************************************************************************/ 537 /* ADC */ 538 #define MXC_BASE_ADC ((uint32_t)0x40034000UL) 539 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) 540 #define MXC_ADC_MAX_CLOCK 8000000 // Maximum ADC clock in Hz 541 542 /******************************************************************************/ 543 /* One Wire Master */ 544 #define MXC_BASE_OWM ((uint32_t)0x4003D000UL) 545 #define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM) 546 547 /******************************************************************************/ 548 /* Semaphore */ 549 #define MXC_CFG_SEMA_INSTANCES (8) 550 551 #define MXC_BASE_SEMA ((uint32_t)0x4003E000UL) 552 #define MXC_SEMA ((mxc_sema_regs_t *)MXC_BASE_SEMA) 553 554 /******************************************************************************/ 555 /* UART / Serial Port Interface */ 556 #define MXC_UART_INSTANCES (4) 557 #define MXC_UART_FIFO_DEPTH (8) 558 559 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL) 560 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) 561 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL) 562 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) 563 #define MXC_BASE_UART2 ((uint32_t)0x40044000UL) 564 #define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2) 565 #define MXC_BASE_UART3 ((uint32_t)0x40081400UL) 566 #define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3) 567 568 #define MXC_UART_GET_IRQ(i) \ 569 (IRQn_Type)((i) == 0 ? UART0_IRQn : \ 570 (IRQn_Type)(i) == 1 ? UART1_IRQn : \ 571 (IRQn_Type)(i) == 2 ? UART2_IRQn : \ 572 (IRQn_Type)(i) == 3 ? UART3_IRQn : \ 573 0) 574 575 #define MXC_UART_GET_BASE(i) \ 576 ((i) == 0 ? MXC_BASE_UART0 : \ 577 (i) == 1 ? MXC_BASE_UART1 : \ 578 (i) == 2 ? MXC_BASE_UART2 : \ 579 (i) == 3 ? MXC_BASE_UART3 : \ 580 0) 581 582 #define MXC_UART_GET_UART(i) \ 583 ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : (i) == 3 ? MXC_UART3 : 0) 584 585 #define MXC_UART_GET_IDX(p) \ 586 ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : (p) == MXC_UART3 ? 3 : -1) 587 588 /******************************************************************************/ 589 /* SPI */ 590 #ifndef __riscv 591 #define MXC_SPI_INSTANCES (2) 592 #else 593 #define MXC_SPI_INSTANCES (1) 594 #endif // __riscv 595 #define MXC_SPI_SS_INSTANCES (4) 596 #define MXC_SPI_FIFO_DEPTH (32) 597 598 #define MXC_BASE_SPI1 ((uint32_t)0x40046000UL) 599 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) 600 #ifndef __riscv 601 #define MXC_BASE_SPI0 ((uint32_t)0x400BE000UL) 602 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) 603 604 // Note: These must be in order SPI1, SPI0 to support RISC-V 605 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI1 ? 0 : (p) == MXC_SPI0 ? 1 : -1) 606 607 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI1 : (i) == 1 ? MXC_BASE_SPI0 : 0) 608 609 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI1 : (i) == 1 ? MXC_SPI0 : 0) 610 611 #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI1_IRQn : (i) == 1 ? SPI0_IRQn : 0) 612 #else // __riscv 613 614 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI1 ? 0 : -1) 615 616 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI1 : 0) 617 618 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI1 : 0) 619 620 #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI1_IRQn : 0) 621 622 #endif // __riscv 623 624 /*******************************************************************************/ 625 /* Pulse Train Generation */ 626 #define MXC_CFG_PT_INSTANCES (4) 627 628 #define MXC_BASE_PTG ((uint32_t)0x4003C000UL) 629 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) 630 #define MXC_BASE_PT0 ((uint32_t)0x4003C020UL) 631 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) 632 #define MXC_BASE_PT1 ((uint32_t)0x4003C040UL) 633 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) 634 #define MXC_BASE_PT2 ((uint32_t)0x4003C060UL) 635 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) 636 #define MXC_BASE_PT3 ((uint32_t)0x4003C080UL) 637 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) 638 639 #define MXC_PT_GET_BASE(i) \ 640 ((i) == 0 ? MXC_BASE_PT0 : \ 641 (i) == 1 ? MXC_BASE_PT1 : \ 642 (i) == 2 ? MXC_BASE_PT2 : \ 643 (i) == 3 ? MXC_BASE_PT3 : \ 644 0) 645 646 #define MXC_PT_GET_PT(i) \ 647 ((i) == 0 ? MXC_PT0 : (i) == 1 ? MXC_PT1 : (i) == 2 ? MXC_PT2 : (i) == 3 ? MXC_PT3 : 0) 648 649 #define MXC_PT_GET_IDX(p) \ 650 ((p) == MXC_PT0 ? 0 : (p) == MXC_PT1 ? 1 : (p) == MXC_PT2 ? 2 : (p) == MXC_PT3 ? 3 : -1) 651 652 /******************************************************************************/ 653 /* TRNG */ 654 #define MXC_BASE_TRNG ((uint32_t)0x4004D000UL) 655 #define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG) 656 657 /******************************************************************************/ 658 /* I2S */ 659 #define MXC_BASE_I2S ((uint32_t)0x40060000UL) 660 #define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) 661 662 /******************************************************************************/ 663 /* Low Power General control */ 664 #define MXC_BASE_LPGCR ((uint32_t)0x40080000UL) 665 #define MXC_LPGCR ((mxc_lpgcr_regs_t *)MXC_BASE_LPGCR) 666 667 /******************************************************************************/ 668 /* Low-Power Comparator */ 669 #define MXC_BASE_LPCMP ((uint32_t)0x40088000UL) 670 #define MXC_LPCMP ((mxc_lpcmp_regs_t *)MXC_BASE_LPCMP) 671 672 /******************************************************************************/ 673 /* Bit Shifting */ 674 #define MXC_F_BIT_0 (1 << 0) 675 #define MXC_F_BIT_1 (1 << 1) 676 #define MXC_F_BIT_2 (1 << 2) 677 #define MXC_F_BIT_3 (1 << 3) 678 #define MXC_F_BIT_4 (1 << 4) 679 #define MXC_F_BIT_5 (1 << 5) 680 #define MXC_F_BIT_6 (1 << 6) 681 #define MXC_F_BIT_7 (1 << 7) 682 #define MXC_F_BIT_8 (1 << 8) 683 #define MXC_F_BIT_9 (1 << 9) 684 #define MXC_F_BIT_10 (1 << 10) 685 #define MXC_F_BIT_11 (1 << 11) 686 #define MXC_F_BIT_12 (1 << 12) 687 #define MXC_F_BIT_13 (1 << 13) 688 #define MXC_F_BIT_14 (1 << 14) 689 #define MXC_F_BIT_15 (1 << 15) 690 #define MXC_F_BIT_16 (1 << 16) 691 #define MXC_F_BIT_17 (1 << 17) 692 #define MXC_F_BIT_18 (1 << 18) 693 #define MXC_F_BIT_19 (1 << 19) 694 #define MXC_F_BIT_20 (1 << 20) 695 #define MXC_F_BIT_21 (1 << 21) 696 #define MXC_F_BIT_22 (1 << 22) 697 #define MXC_F_BIT_23 (1 << 23) 698 #define MXC_F_BIT_24 (1 << 24) 699 #define MXC_F_BIT_25 (1 << 25) 700 #define MXC_F_BIT_26 (1 << 26) 701 #define MXC_F_BIT_27 (1 << 27) 702 #define MXC_F_BIT_28 (1 << 28) 703 #define MXC_F_BIT_29 (1 << 29) 704 #define MXC_F_BIT_30 (1 << 30) 705 #define MXC_F_BIT_31 (1 << 31) 706 707 /******************************************************************************/ 708 /* Bit Banding */ 709 #define BITBAND(reg, bit) \ 710 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ 711 ((bit) << 2)) 712 713 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) 714 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) 715 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) 716 717 #define MXC_SETFIELD(reg, mask, setting) ((reg) = ((reg) & ~(mask)) | ((setting) & (mask))) 718 719 /******************************************************************************/ 720 /* SCB CPACR */ 721 722 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ 723 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ 724 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ 725 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ 726 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ 727 728 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_MAX32655_H_ 729
