Home
last modified time | relevance | path

Searched refs:reset (Results 1 – 25 of 1344) sorted by relevance

12345678910>>...54

/Zephyr-latest/samples/drivers/espi/boards/
Dmec172xevb_assy6906.overlay24 reset-state = "1";
25 reset-source = "ESPI_RESET";
30 reset-state = "1";
31 reset-source = "ESPI_RESET";
36 reset-state = "1";
37 reset-source = "ESPI_RESET";
42 reset-state = "1";
43 reset-source = "ESPI_RESET";
Dmec172xmodular_assy6930.overlay21 reset-state = "1";
22 reset-source = "ESPI_RESET";
27 reset-state = "1";
28 reset-source = "ESPI_RESET";
33 reset-state = "1";
34 reset-source = "ESPI_RESET";
39 reset-state = "1";
40 reset-source = "ESPI_RESET";
/Zephyr-latest/doc/hardware/peripherals/
Dreset.rst9 Reset controllers are units that control the reset signals to multiple
10 peripherals. The reset controller API allows peripheral drivers to request
11 control over their reset input signals, including the ability to assert,
12 deassert and toggle those signals. Also, the reset status of the reset input
16 in most cases we want to toggle the reset signals.
/Zephyr-latest/scripts/west_commands/runners/
Dminichlink.py20 reset: bool,
28 self.reset = reset
38 return RunnerCaps(commands={"flash"}, flash_addr=True, erase=True, reset=True)
51 parser.set_defaults(reset=True)
59 reset=args.reset,
86 if self.reset or self.terminal:
Dstm32flash.py21 serial_mode='8e1', reset=False, verify=False): argument
31 self.reset = reset
40 return RunnerCaps(commands={'flash'}, reset=True)
78 parser.set_defaults(reset=False)
85 serial_mode=args.serial_mode, reset=args.reset, verify=args.verify)
135 if self.reset:
Dezflashcli.py15 def __init__(self, cfg, tool, dev_id=None, tool_opt=None, erase=False, reset=True): argument
22 self.reset = bool(reset)
35 return RunnerCaps(commands={'flash'}, dev_id=True, tool_opt=True, erase=True, reset=True)
51 parser.set_defaults(reset=True)
101 if self.reset:
Desp32.py19 app_address, erase=False, reset=False, baud=921600, argument
27 self.reset = bool(reset)
47 return RunnerCaps(commands={'flash'}, erase=True, reset=True)
84 parser.set_defaults(reset=True)
97 app_address=args.esp_app_address, erase=args.erase, reset=args.reset,
121 if self.reset:
/Zephyr-latest/dts/arm64/intel/
Dintel_socfpga_agilex5.dtsi10 #include <zephyr/dt-bindings/reset/intel_socfpga_reset.h>
113 resets = <&reset RSTMGR_UART0_RSTLINE>;
117 reset: reset-controller@10D11000 { label
118 compatible = "intel,socfpga-reset";
121 #reset-cells = <1>;
132 resets = <&reset RSTMGR_SDMMC_RSTLINE>,
133 <&reset RSTMGR_SDMMCECC_RSTLINE>,
134 <&reset RSTMGR_SOFTPHY_RSTLINE>;
145 resets = <&reset RSTMGR_SPTIMER0_RSTLINE>;
156 resets = <&reset RSTMGR_SPTIMER1_RSTLINE>;
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc51u68.dtsi12 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
30 reset: reset { label
31 compatible = "nxp,lpc-syscon-reset";
32 #reset-cells = <1>;
101 resets = <&reset NXP_SYSCON_RESET(1, 11)>;
110 resets = <&reset NXP_SYSCON_RESET(1, 12)>;
119 resets = <&reset NXP_SYSCON_RESET(1, 13)>;
128 resets = <&reset NXP_SYSCON_RESET(1, 14)>;
137 resets = <&reset NXP_SYSCON_RESET(1, 15)>;
146 resets = <&reset NXP_SYSCON_RESET(1, 16)>;
[all …]
Dnxp_lpc55S0x_common.dtsi11 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
72 reset: reset { label
73 compatible = "nxp,lpc-syscon-reset";
74 #reset-cells = <1>;
159 resets = <&reset NXP_SYSCON_RESET(1, 11)>;
168 resets = <&reset NXP_SYSCON_RESET(1, 12)>;
177 resets = <&reset NXP_SYSCON_RESET(1, 13)>;
186 resets = <&reset NXP_SYSCON_RESET(1, 14)>;
195 resets = <&reset NXP_SYSCON_RESET(1, 15)>;
204 resets = <&reset NXP_SYSCON_RESET(1, 16)>;
[all …]
Dnxp_lpc54xxx.dtsi12 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
45 reset: reset { label
46 compatible = "nxp,lpc-syscon-reset";
47 #reset-cells = <1>;
164 resets = <&reset NXP_SYSCON_RESET(1, 11)>;
173 resets = <&reset NXP_SYSCON_RESET(1, 12)>;
182 resets = <&reset NXP_SYSCON_RESET(1, 13)>;
191 resets = <&reset NXP_SYSCON_RESET(1, 14)>;
200 resets = <&reset NXP_SYSCON_RESET(1, 15)>;
209 resets = <&reset NXP_SYSCON_RESET(1, 16)>;
[all …]
/Zephyr-latest/drivers/watchdog/
DKconfig.smartbond15 bool "NMI pre-reset interrupt enable"
21 reset at <= -16. Timer can be frozen/resumed using
25 reset at value 0 and can not be frozen by Software.
27 only be reset with a WDOG (SYS) reset or SW reset.
/Zephyr-latest/tests/drivers/build_all/modem/
Duart.dtsi11 mdm-reset-gpios = <&test_gpio 0 0>;
26 mdm-reset-gpios = <&test_gpio 0 0>;
34 mdm-reset-gpios = <&test_gpio 0 0>;
47 mdm-reset-gpios = <&test_gpio 0 0>;
53 mdm-reset-gpios = <&test_gpio 0 0>;
60 mdm-reset-gpios = <&test_gpio 0 0>;
79 mdm-reset-gpios = <&test_gpio 0 0>;
/Zephyr-latest/boards/st/stm32h573i_dk/support/
Dopenocd.cfg11 # use hardware reset, connect under reset
18 # to reset halt just after openocd init.
22 reset halt
/Zephyr-latest/boards/st/nucleo_h503rb/support/
Dopenocd.cfg11 # use hardware reset, connect under reset
18 # to reset halt just after openocd init.
22 reset halt
/Zephyr-latest/boards/st/nucleo_h533re/support/
Dopenocd.cfg11 # use hardware reset, connect under reset
18 # to reset halt just after openocd init.
22 reset halt
/Zephyr-latest/boards/st/nucleo_h563zi/support/
Dopenocd.cfg11 # use hardware reset, connect under reset
18 # to reset halt just after openocd init.
22 reset halt
/Zephyr-latest/boards/st/stm32f7508_dk/support/
Dopenocd.cfg5 reset halt
14 # Event reset-init already uses the maximum speed however adapter speed
15 # inherited from stm32f7x.cfg for reset-start defaults to 2000 kHz, so
17 $_TARGETNAME configure -event reset-start {
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_samr3x_radio_off.c14 const struct gpio_dt_spec reset = GPIO_DT_SPEC_GET(DT_NODELABEL(lora), reset_gpios); in radio_off_setup() local
17 if (!gpio_is_ready_dt(&reset) || !gpio_is_ready_dt(&cs)) { in radio_off_setup()
21 ret = gpio_pin_configure_dt(&reset, GPIO_OUTPUT_ACTIVE); in radio_off_setup()
/Zephyr-latest/boards/st/stm32f746g_disco/support/
Dopenocd.cfg5 reset halt
18 # Event reset-init already uses the maximum speed however adapter speed
19 # inherited from stm32f7x.cfg for reset-start defaults to 2000 kHz, so
21 $_TARGETNAME configure -event reset-start {
/Zephyr-latest/drivers/mipi_dbi/
Dmipi_dbi_stm32_fmc.c21 const struct gpio_dt_spec reset; member
130 if (config->reset.port == NULL) { in mipi_dbi_stm32_fmc_reset()
134 ret = gpio_pin_set_dt(&config->reset, 1); in mipi_dbi_stm32_fmc_reset()
141 return gpio_pin_set_dt(&config->reset, 0); in mipi_dbi_stm32_fmc_reset()
148 if (config->reset.port) { in mipi_dbi_stm32_fmc_init()
149 if (!gpio_is_ready_dt(&config->reset)) { in mipi_dbi_stm32_fmc_init()
154 if (gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT_INACTIVE)) { in mipi_dbi_stm32_fmc_init()
176 .reset = mipi_dbi_stm32_fmc_reset,
189 .reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {}), \
/Zephyr-latest/drivers/reset/
DKconfig.npcx1 # NPCX reset controller driver configuration options
7 bool "Nuvoton NPCX embedded controller (EC) reset controller driver"
11 This option enables the reset controller driver for Nuvoton NPCX MCUs.
/Zephyr-latest/drivers/bbram/
DKconfig.stm3215 powered-on by VBAT when the VDD power is switched off. They are not reset
16 by system reset or when the device wakes up from Standby mode. They are
17 reset by a backup domain reset.
/Zephyr-latest/boards/silabs/dev_kits/sim3u1xx_dk/support/
Dopenocd.cfg10 # On SiM3U1xx, doing a chip reset also takes down the debug port. For this reason, we disable the
11 # chip reset and instead only reset the Cortex M via the AIRCR SYSRESETREQ bit, as suggested in the
17 reset halt
/Zephyr-latest/boards/gardena/sgrm/support/
Dopenocd.cfg10 # On SiM3U1xx, doing a chip reset also takes down the debug port. For this reason, we disable the
11 # chip reset and instead only reset the Cortex M via the AIRCR SYSRESETREQ bit, as suggested in the
17 reset halt

12345678910>>...54