Lines Matching refs:reset
10 #include <zephyr/dt-bindings/reset/intel_socfpga_reset.h>
113 resets = <&reset RSTMGR_UART0_RSTLINE>;
117 reset: reset-controller@10D11000 { label
118 compatible = "intel,socfpga-reset";
121 #reset-cells = <1>;
132 resets = <&reset RSTMGR_SDMMC_RSTLINE>,
133 <&reset RSTMGR_SDMMCECC_RSTLINE>,
134 <&reset RSTMGR_SOFTPHY_RSTLINE>;
145 resets = <&reset RSTMGR_SPTIMER0_RSTLINE>;
156 resets = <&reset RSTMGR_SPTIMER1_RSTLINE>;
167 resets = <&reset RSTMGR_L4SYSTIMER0_RSTLINE>;
178 resets = <&reset RSTMGR_L4SYSTIMER1_RSTLINE>;
185 resets = <&reset RSTMGR_WATCHDOG0_RSTLINE>;
193 resets = <&reset RSTMGR_WATCHDOG1_RSTLINE>;
201 resets = <&reset RSTMGR_WATCHDOG2_RSTLINE>;
209 resets = <&reset RSTMGR_WATCHDOG3_RSTLINE>;
217 resets = <&reset RSTMGR_WATCHDOG4_RSTLINE>;
236 resets = <&reset RSTMGR_NAND_RSTLINE>,
237 <&reset RSTMGR_SOFTPHY_RSTLINE>;
257 resets = <&reset RSTMGR_DMA_RSTLINE>;
275 resets = <&reset RSTMGR_DMA_RSTLINE>;
297 resets = <&reset RSTMGR_TSN0_RSTLINE>;
321 resets = <&reset RSTMGR_TSN1_RSTLINE>;
345 resets = <&reset RSTMGR_TSN2_RSTLINE>;