| /Zephyr-latest/dts/riscv/microchip/ |
| D | mpfs.dtsi | 117 plic: interrupt-controller@c000000 { label
118 compatible = "sifive,plic-1.0.0";
136 interrupt-parent = <&plic>;
147 interrupt-parent = <&plic>;
158 interrupt-parent = <&plic>;
169 interrupt-parent = <&plic>;
180 interrupt-parent = <&plic>;
191 interrupt-parent = <&plic>;
202 interrupt-parent = <&plic>;
213 interrupt-parent = <&plic>;
[all …]
|
| D | microchip-miv.dtsi | 51 plic: interrupt-controller@40000000 { label
52 compatible = "sifive,plic-1.0.0";
|
| /Zephyr-latest/dts/riscv/sifive/ |
| D | riscv32-fe310.dtsi | 51 interrupt-parent = <&plic>;
58 interrupt-parent = <&plic>;
87 interrupt-parent = <&plic>;
112 interrupt-parent = <&plic>;
120 plic: interrupt-controller@c000000 { label
121 compatible = "sifive,plic-1.0.0";
147 interrupt-parent = <&plic>;
157 interrupt-parent = <&plic>;
167 interrupt-parent = <&plic>;
187 interrupt-parent = <&plic>;
[all …]
|
| D | riscv64-fu740.dtsi | 147 plic: interrupt-controller@c000000 { label
148 compatible = "sifive,plic-1.0.0";
164 interrupt-parent = <&plic>;
173 interrupt-parent = <&plic>;
182 interrupt-parent = <&plic>;
193 interrupt-parent = <&plic>;
204 interrupt-parent = <&plic>;
|
| D | riscv64-fu540.dtsi | 191 plic: interrupt-controller@c000000 { label
192 compatible = "sifive,plic-1.0.0";
208 interrupt-parent = <&plic>;
217 interrupt-parent = <&plic>;
226 interrupt-parent = <&plic>;
237 interrupt-parent = <&plic>;
248 interrupt-parent = <&plic>;
261 interrupt-parent = <&plic>;
|
| /Zephyr-latest/dts/riscv/starfive/ |
| D | starfive_jh7100_beagle_v.dtsi | 98 interrupt-parent = <&plic>;
124 plic: plic@c000000 { label
125 compatible = "sifive,plic-1.0.0";
138 interrupt-parent = <&plic>;
151 interrupt-parent = <&plic>;
164 interrupt-parent = <&plic>;
177 interrupt-parent = <&plic>;
|
| D | jh7110-visionfive-v2.dtsi | 165 interrupt-parent = <&plic>;
170 plic: interrupt-controller@c000000 { label
171 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
191 interrupt-parent = <&plic>;
204 interrupt-parent = <&plic>;
|
| /Zephyr-latest/tests/drivers/interrupt_controller/intc_plic/ |
| D | alt_mapping.overlay | 9 plic: interrupt-controller@c000000 {
24 compatible = "sifive,plic-1.0.0";
|
| /Zephyr-latest/dts/riscv/lowrisc/ |
| D | opentitan_earlgrey.dtsi | 60 interrupt-parent = <&plic>;
71 plic: interrupt-controller@48000000 { label
72 compatible = "sifive,plic-1.0.0";
|
| /Zephyr-latest/dts/riscv/ |
| D | renode_riscv32_virt.dtsi | 54 compatible = "sifive,plic-1.0.0";
65 compatible = "sifive,plic-1.0.0";
|
| /Zephyr-latest/boards/snps/nsim/arc_v/support/ |
| D | rmx100.props | 6 nsim_mem-dev=plic,base=0xc000000,size=0x04000000,interrupts=128,priorities=16
|
| /Zephyr-latest/tests/drivers/build_all/interrupt_controller/intc_plic/ |
| D | app.multi_instance.overlay | 24 compatible = "sifive,plic-1.0.0";
|
| /Zephyr-latest/dts/riscv/qemu/ |
| D | virt-riscv.dtsi | 29 interrupt-parent = < &plic >;
164 plic: interrupt-controller@c000000 { label
179 compatible = "sifive,plic-1.0.0";
|
| /Zephyr-latest/dts/riscv/efinix/ |
| D | sapphire_soc.dtsi | 52 compatible = "sifive,plic-1.0.0";
|
| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_plic.c | 617 const struct device **plic) in parse_device() argument
621 *plic = device_get_binding(argv[1]); in parse_device()
622 if (*plic == NULL) { in parse_device()
856 SHELL_CMD_REGISTER(plic, &plic_cmds, "PLIC shell commands", NULL);
932 plic##n, DEVICE_DT_INST_GET(n), DT_INST_IRQN(n), \
|
| D | Kconfig | 95 source "drivers/interrupt_controller/Kconfig.plic"
|
| /Zephyr-latest/dts/riscv/andes/ |
| D | andes_v5_ae350.dtsi | 169 compatible = "sifive,plic-1.0.0", "andestech,nceplic100";
183 compatible = "sifive,plic-1.0.0", "andestech,nceplic100";
197 compatible = "andestech,mbox-plic-sw";
|
| /Zephyr-latest/dts/riscv/telink/ |
| D | telink_b91.dtsi | 129 compatible = "sifive,plic-1.0.0";
|
| /Zephyr-latest/doc/releases/ |
| D | migration-guide-3.6.rst | 172 plic: interrupt-controller@c000000 {
178 compatible = "sifive,plic-1.0.0";
185 interrupt-parent = <&plic>;
192 ``plic`` is a second level interrupt aggregator and ``uart0`` is a child of ``plic``.
|
| D | release-notes-1.13.rst | 474 …b:`8699` - [Coverity CID :186842] Memory - illegal accesses in /drivers/interrupt_controller/plic.c
|
| D | release-notes-2.1.rst | 224 * Converted RISC-V plic to use multi-level irq support
|
| D | release-notes-3.5.rst | 1143 * :dtcompatible:`andestech,plic-sw`
|
