Home
last modified time | relevance | path

Searched refs:clock_div (Results 1 – 23 of 23) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_control_ifx_cat1.c274 uint32_t clock_div) in _configure_clk_hf() argument
285 rslt = cyhal_clock_set_divider(clock_obj, clock_div); in _configure_clk_hf()
390 uint32 clock_div; in clock_control_infineon_cat1_init() local
501 clock_div = DT_PROP(DT_NODELABEL(clk_hf0), clock_div); in clock_control_infineon_cat1_init()
503 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[0], clock_div)) { in clock_control_infineon_cat1_init()
512 clock_div = DT_PROP(DT_NODELABEL(clk_hf1), clock_div); in clock_control_infineon_cat1_init()
514 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[1], clock_div)) { in clock_control_infineon_cat1_init()
523 clock_div = DT_PROP(DT_NODELABEL(clk_hf2), clock_div); in clock_control_infineon_cat1_init()
525 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[2], clock_div)) { in clock_control_infineon_cat1_init()
534 clock_div = DT_PROP(DT_NODELABEL(clk_hf3), clock_div); in clock_control_infineon_cat1_init()
[all …]
Dclock_control_rpi_pico.c61 #define REF_DIV(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), clock_div)
924 .ref_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), clock_div),
930 .ref_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), clock_div),
944 .div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), clock_div),
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dsoc.c32 BUILD_ASSERT(DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) >= (a) && \
33 DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) <= (b), \
180 CLOCK_SetDiv(kCLOCK_ArmDiv, DT_PROP(DT_CHILD(CCM_NODE, arm_podf), clock_div) - 1); in clock_init()
184 CLOCK_SetDiv(kCLOCK_AhbDiv, DT_PROP(DT_CHILD(CCM_NODE, ahb_podf), clock_div) - 1); in clock_init()
187 CLOCK_SetDiv(kCLOCK_IpgDiv, DT_PROP(DT_CHILD(CCM_NODE, ipg_podf), clock_div) - 1); in clock_init()
/Zephyr-latest/soc/sifive/sifive_freedom/fe300/
Dsoc.h20 #define SIFIVE_TLCLK_DIVIDER DT_PROP(DT_NODELABEL(tlclk), clock_div)
Dclock.c13 BUILD_ASSERT(DT_PROP(DT_NODELABEL(tlclk), clock_div) == 1,
/Zephyr-latest/soc/sifive/sifive_freedom/fu500/
Dsoc.h20 #define SIFIVE_TLCLK_DIVIDER DT_PROP(DT_NODELABEL(tlclk), clock_div)
Dclock.c14 BUILD_ASSERT(DT_PROP(DT_NODELABEL(tlclk), clock_div) == 2,
/Zephyr-latest/soc/nxp/kinetis/kwx/
Dsoc_kw4xz.c22 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
Dsoc_kw2xd.c33 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
/Zephyr-latest/soc/nxp/kinetis/k2x/
Dsoc.c34 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
/Zephyr-latest/soc/nxp/kinetis/kl2x/
Dsoc.c21 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
/Zephyr-latest/soc/nxp/kinetis/kv5x/
Dsoc.c26 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
/Zephyr-latest/drivers/adc/
Dadc_mcux_adc12.c27 adc12_clock_divider_t clock_div; member
237 adc_config.clockDivider = config->clock_div; in mcux_adc12_init()
294 .clock_div = \
Dadc_mcux_gau_adc.c26 adc_clock_divider_t clock_div; member
320 adc_config.clockDivider = config->clock_div; in mcux_gau_adc_init()
372 .clock_div = DT_INST_PROP(n, nxp_clock_divider) - 1, \
/Zephyr-latest/modules/hal_silabs/simplicity_sdk/config/
Dsl_clock_manager_tree_config.h41 CONCAT(CMU_SYSCLKCTRL_HCLKPRESC_DIV, DT_PROP(DT_NODELABEL(hclk), clock_div))
44 CONCAT(CMU_SYSCLKCTRL_PCLKPRESC_DIV, DT_PROP(DT_NODELABEL(pclk), clock_div))
79 #if DT_NODE_HAS_PROP(DT_NODELABEL(traceclk), clock_div)
81 CONCAT(CMU_TRACECLKCTRL_PRESC_DIV, DT_PROP(DT_NODELABEL(traceclk), clock_div))
/Zephyr-latest/soc/nxp/kinetis/k8x/
Dsoc.c29 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
/Zephyr-latest/drivers/memc/
Dmemc_smartbond_nor_psram.c147 memc_set_status(true, DT_INST_PROP_OR(0, clock_div, 0)); in memc_smartbond_init()
221 memc_set_status(true, DT_INST_PROP_OR(0, clock_div, 0)); in memc_smartbond_pm_action()
/Zephyr-latest/soc/nxp/kinetis/k6x/
Dsoc.c36 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
/Zephyr-latest/soc/nxp/mcx/mcxc/
Dsoc.c30 #define CLOCK_DIVIDER(clk) DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
/Zephyr-latest/drivers/spi/
Dspi_rpi_pico_pio.c306 float clock_div = spi_pico_pio_clock_divisor(clock_freq, SPI_SIO_MODE_0_0_TX_CYCLES, in spi_pico_pio_configure() local
321 sm_config_set_clkdiv(&sm_config, clock_div); in spi_pico_pio_configure()
381 float clock_div = in spi_pico_pio_configure() local
391 sm_config_set_clkdiv(&sm_config, clock_div); in spi_pico_pio_configure()
/Zephyr-latest/soc/nxp/kinetis/ke1xz/
Dsoc.c31 #define SCG_CLOCK_DIV(name) DT_PROP(SCG_CLOCK_NODE(name), clock_div)
/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dsoc.c73 BUILD_ASSERT(DT_NODE_HAS_PROP(DT_NODELABEL(arm_pll), clock_div),
79 DT_PROP_OR(DT_NODELABEL(arm_pll), clock_div, DEFAULT_POSTDIV)),
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dsoc.c31 #define SCG_CLOCK_DIV(name) DT_PROP(SCG_CLOCK_NODE(name), clock_div)