| /Zephyr-latest/drivers/pwm/ |
| D | pwm_led_esp32.c | 74 static void pwm_led_esp32_low_speed_update(const struct device *dev, int speed_mode, int channel) in pwm_led_esp32_low_speed_update() argument
79 ledc_hal_ls_channel_update(&data->hal, channel); in pwm_led_esp32_low_speed_update()
83 static void pwm_led_esp32_update_duty(const struct device *dev, int speed_mode, int channel) in pwm_led_esp32_update_duty() argument
87 ledc_hal_set_sig_out_en(&data->hal, channel, true); in pwm_led_esp32_update_duty()
88 ledc_hal_set_duty_start(&data->hal, channel, true); in pwm_led_esp32_update_duty()
90 pwm_led_esp32_low_speed_update(dev, speed_mode, channel); in pwm_led_esp32_update_duty()
94 struct pwm_ledc_esp32_channel_config *channel) in pwm_led_esp32_duty_set() argument
98 ledc_hal_set_hpoint(&data->hal, channel->channel_num, 0); in pwm_led_esp32_duty_set()
99 ledc_hal_set_duty_int_part(&data->hal, channel->channel_num, channel->duty_val); in pwm_led_esp32_duty_set()
100 ledc_hal_set_duty_direction(&data->hal, channel->channel_num, 1); in pwm_led_esp32_duty_set()
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| D | pwm_mc_esp32.c | 103 struct mcpwm_esp32_channel_config *channel) in mcpwm_esp32_duty_set() argument
110 if (channel->inverted) { in mcpwm_esp32_duty_set()
111 duty_type = channel->duty == 0 ? in mcpwm_esp32_duty_set()
112 MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH : channel->duty == 100 ? in mcpwm_esp32_duty_set()
115 duty_type = channel->duty == 0 ? in mcpwm_esp32_duty_set()
116 MCPWM_HAL_GENERATOR_MODE_FORCE_LOW : channel->duty == 100 ? in mcpwm_esp32_duty_set()
120 uint32_t timer_clk_hz = data->mcpwm_clk_hz / config->prescale / channel->prescale; in mcpwm_esp32_duty_set()
122 set_duty = (timer_clk_hz / channel->freq) * channel->duty / 100; in mcpwm_esp32_duty_set()
123 mcpwm_ll_operator_connect_timer(data->hal.dev, channel->operator_id, channel->timer_id); in mcpwm_esp32_duty_set()
124 mcpwm_ll_operator_set_compare_value(data->hal.dev, channel->operator_id, in mcpwm_esp32_duty_set()
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| D | pwm_mcux_sctimer.c | 36 sctimer_pwm_signal_param_t channel[CHANNEL_COUNT]; member
43 uint32_t channel, uint32_t period_cycles, in mcux_sctimer_new_channel() argument
68 data->channel[channel].dutyCyclePercent = duty_cycle; in mcux_sctimer_new_channel()
69 if (SCTIMER_SetupPwm(config->base, &data->channel[channel], in mcux_sctimer_new_channel()
71 clock_freq, &data->event_number[channel]) == kStatus_Fail) { in mcux_sctimer_new_channel()
82 uint32_t channel, uint32_t period_cycles, in mcux_sctimer_pwm_set_cycles() argument
90 if (channel >= CHANNEL_COUNT) { in mcux_sctimer_pwm_set_cycles()
101 data->channel[channel].level = kSCTIMER_HighTrue; in mcux_sctimer_pwm_set_cycles()
103 data->channel[channel].level = kSCTIMER_LowTrue; in mcux_sctimer_pwm_set_cycles()
118 if (data->channel[channel].level == kSCTIMER_HighTrue) { in mcux_sctimer_pwm_set_cycles()
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| D | pwm_nxp_s32_emios.c | 86 static int pwm_nxp_s32_set_cycles_internal_timebase(uint8_t instance, uint32_t channel, in pwm_nxp_s32_set_cycles_internal_timebase() argument
97 if (Emios_Pwm_Ip_GetPeriod(instance, channel) != period_cycles) { in pwm_nxp_s32_set_cycles_internal_timebase()
98 Emios_Pwm_Ip_SetPeriod(instance, channel, period_cycles); in pwm_nxp_s32_set_cycles_internal_timebase()
102 if (Emios_Pwm_Ip_GetDutyCycle(instance, channel) != pulse_cycles) { in pwm_nxp_s32_set_cycles_internal_timebase()
104 if (Emios_Pwm_Ip_SetDutyCycle(instance, channel, pulse_cycles)) { in pwm_nxp_s32_set_cycles_internal_timebase()
112 Emios_Pwm_Ip_ForceMatchTrailingEdge(instance, channel, true); in pwm_nxp_s32_set_cycles_internal_timebase()
120 static int pwm_nxp_s32_set_cycles_external_timebase(uint8_t instance, uint32_t channel, in pwm_nxp_s32_set_cycles_external_timebase() argument
131 if (Emios_Pwm_Ip_GetPeriod(instance, channel) != period_cycles) { in pwm_nxp_s32_set_cycles_external_timebase()
136 master_channel = Emios_Pwm_Ip_GetMasterBusChannel(instance, channel); in pwm_nxp_s32_set_cycles_external_timebase()
144 if (Emios_Pwm_Ip_GetDutyCycle(instance, channel) != pulse_cycles) { in pwm_nxp_s32_set_cycles_external_timebase()
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| D | pwm_mcux_tpm.c | 45 tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS]; member
48 static int mcux_tpm_set_cycles(const struct device *dev, uint32_t channel, in mcux_tpm_set_cycles() argument
61 if (channel >= config->channel_count) { in mcux_tpm_set_cycles()
67 data->channel[channel].dutyCyclePercent = duty_cycle; in mcux_tpm_set_cycles()
70 data->channel[channel].level = kTPM_HighTrue; in mcux_tpm_set_cycles()
72 data->channel[channel].level = kTPM_LowTrue; in mcux_tpm_set_cycles()
105 status = TPM_SetupPwm(config->base, data->channel, in mcux_tpm_set_cycles()
115 TPM_UpdateChnlEdgeLevelSelect(config->base, channel, in mcux_tpm_set_cycles()
116 data->channel[channel].level); in mcux_tpm_set_cycles()
117 TPM_UpdatePwmDutycycle(config->base, channel, config->mode, in mcux_tpm_set_cycles()
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| D | pwm_rv32m1_tpm.c | 40 tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS]; member
43 static int rv32m1_tpm_set_cycles(const struct device *dev, uint32_t channel, in rv32m1_tpm_set_cycles() argument
56 if (channel >= config->channel_count) { in rv32m1_tpm_set_cycles()
62 data->channel[channel].dutyCyclePercent = duty_cycle; in rv32m1_tpm_set_cycles()
65 data->channel[channel].level = kTPM_HighTrue; in rv32m1_tpm_set_cycles()
67 data->channel[channel].level = kTPM_LowTrue; in rv32m1_tpm_set_cycles()
100 status = TPM_SetupPwm(config->base, data->channel, in rv32m1_tpm_set_cycles()
110 TPM_UpdateChnlEdgeLevelSelect(config->base, channel, in rv32m1_tpm_set_cycles()
111 data->channel[channel].level); in rv32m1_tpm_set_cycles()
112 TPM_UpdatePwmDutycycle(config->base, channel, config->mode, in rv32m1_tpm_set_cycles()
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| /Zephyr-latest/tests/boards/intel_adsp/hda/src/ |
| D | dma.c | 47 int res, channel; in ZTEST() local
73 channel = dma_request_channel(dma, NULL); in ZTEST()
74 zassert_true(channel >= 0, "Expected a valid DMA channel"); in ZTEST()
75 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, channel, "dma channel"); in ZTEST()
77 hda_ipc_msg(INTEL_ADSP_IPC_HOST_DEV, IPCCMD_HDA_RESET, channel, IPC_TIMEOUT); in ZTEST()
78 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, channel, "host reset"); in ZTEST()
81 channel | (DMA_BUF_SIZE << 8), IPC_TIMEOUT); in ZTEST()
82 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, channel, "host config"); in ZTEST()
96 res = dma_config(dma, channel, &dma_cfg); in ZTEST()
97 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, channel, "dsp dma config"); in ZTEST()
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| /Zephyr-latest/drivers/dma/ |
| D | dma_sam_xdmac.c | 64 for (int channel = 0; channel < DMA_CHANNELS_NO; channel++) { in sam_xdmac_isr() local
65 if (!(isr_status & (1 << channel))) { in sam_xdmac_isr()
69 channel_cfg = &dev_data->dma_channels[channel]; in sam_xdmac_isr()
72 err = xdmac->XDMAC_CHID[channel].XDMAC_CIS & XDMAC_INT_ERR; in sam_xdmac_isr()
77 channel, err); in sam_xdmac_isr()
82 int sam_xdmac_channel_configure(const struct device *dev, uint32_t channel, in sam_xdmac_channel_configure() argument
89 if (channel >= DMA_CHANNELS_NO) { in sam_xdmac_channel_configure()
94 if (xdmac->XDMAC_GS & (XDMAC_GS_ST0 << channel)) { in sam_xdmac_channel_configure()
99 xdmac->XDMAC_CHID[channel].XDMAC_CID = 0xFF; in sam_xdmac_channel_configure()
101 (void)xdmac->XDMAC_CHID[channel].XDMAC_CIS; in sam_xdmac_channel_configure()
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| D | dma_xmc4xxx.c | 54 int channel = find_lsb_set(channels_event) - 1; \
57 __ASSERT_NO_MSG(channel >= 0); \
58 dma_channel = &dev_data->channels[channel]; \
61 XMC_DMA_CH_ClearEventStatus(dma, channel, XMC_DMA_CH_##event_test); \
63 dma_channel->cb(dev, dma_channel->user_data, channel, (ret)); \
123 static int dma_xmc4xxx_config(const struct device *dev, uint32_t channel, struct dma_config *config) in dma_xmc4xxx_config() argument
131 if (channel >= dev_data->ctx.dma_channels) { in dma_xmc4xxx_config()
159 if (dma != XMC_DMA0 || channel >= 2) { in dma_xmc4xxx_config()
194 if (XMC_DMA_CH_IsEnabled(dma, channel)) { in dma_xmc4xxx_config()
199 XMC_DMA_CH_ClearEventStatus(dma, channel, ALL_EVENTS); in dma_xmc4xxx_config()
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| D | dma_andes_atcdmac300.c | 151 uint32_t int_status, int_ch_status, channel; in dma_atcdmac300_isr() local
166 channel = find_msb_set(int_ch_status) - 1; in dma_atcdmac300_isr()
167 int_ch_status &= ~(BIT(channel)); in dma_atcdmac300_isr()
169 ch_data = &data->chan[channel]; in dma_atcdmac300_isr()
171 ch_data->blkcallback(dev, ch_data->blkuser_data, channel, 0); in dma_atcdmac300_isr()
173 data->chan[channel].status.busy = false; in dma_atcdmac300_isr()
179 channel = find_msb_set(int_ch_status) - 1; in dma_atcdmac300_isr()
180 int_ch_status &= ~(BIT(channel)); in dma_atcdmac300_isr()
182 ch_data = &data->chan[channel]; in dma_atcdmac300_isr()
184 ch_data->blkcallback(dev, ch_data->blkuser_data, channel, -EIO); in dma_atcdmac300_isr()
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| D | dma_si32.c | 57 static void dma_si32_isr_handler(const uint8_t channel) in dma_si32_isr_handler() argument
59 const struct SI32_DMADESC_A_Struct *channel_descriptor = &channel_descriptors[channel]; in dma_si32_isr_handler()
60 const dma_callback_t cb = dma_si32_data.channel_data[channel].callback; in dma_si32_isr_handler()
61 void *user_data = dma_si32_data.channel_data[channel].callback_user_data; in dma_si32_isr_handler()
64 LOG_INF("Channel %" PRIu8 " ISR fired", channel); in dma_si32_isr_handler()
66 irq_disable(DMACH0_IRQn + channel); in dma_si32_isr_handler()
69 LOG_ERR("Bus error on channel %" PRIu8, channel); in dma_si32_isr_handler()
77 __ASSERT((SI32_DMACTRL_0->CHENSET.U32 & BIT(channel)) == 0, in dma_si32_isr_handler()
85 cb(DEVICE_DT_INST_GET(0), user_data, channel, result); in dma_si32_isr_handler()
88 #define DMA_SI32_IRQ_CONNECT(channel) \ argument
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| D | dma_intel_adsp_hda.c | 31 uint32_t channel, in intel_adsp_hda_dma_host_in_config() argument
39 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_host_in_config()
49 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_host_in_config()
53 *DGMBS(cfg->base, cfg->regblock_size, channel) = in intel_adsp_hda_dma_host_in_config()
56 intel_adsp_hda_set_sample_container_size(cfg->base, cfg->regblock_size, channel, in intel_adsp_hda_dma_host_in_config()
65 uint32_t channel, in intel_adsp_hda_dma_host_out_config() argument
73 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_host_out_config()
84 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_host_out_config()
88 *DGMBS(cfg->base, cfg->regblock_size, channel) = in intel_adsp_hda_dma_host_out_config()
91 intel_adsp_hda_set_sample_container_size(cfg->base, cfg->regblock_size, channel, in intel_adsp_hda_dma_host_out_config()
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| D | dma_dw_common.c | 37 uint32_t channel; in dw_dma_isr() local
61 channel = find_lsb_set(status_block) - 1; in dw_dma_isr()
62 status_block &= ~(1 << channel); in dw_dma_isr()
63 chan_data = &dev_data->chan[channel]; in dw_dma_isr()
67 channel); in dw_dma_isr()
75 channel, DMA_STATUS_BLOCK); in dw_dma_isr()
80 channel = find_lsb_set(status_tfr) - 1; in dw_dma_isr()
81 status_tfr &= ~(1 << channel); in dw_dma_isr()
82 chan_data = &dev_data->chan[channel]; in dw_dma_isr()
92 channel); in dw_dma_isr()
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| D | dma_max32.c | 77 static int max32_dma_config(const struct device *dev, uint32_t channel, struct dma_config *config) in max32_dma_config() argument
84 if (channel >= cfg->channels) { in max32_dma_config()
86 channel); in max32_dma_config()
90 ch = max32_dma_ch_index(cfg->regs, channel); in max32_dma_config()
149 data[channel].callback = config->dma_callback; in max32_dma_config()
150 data[channel].cb_data = config->user_data; in max32_dma_config()
151 data[channel].err_cb_dis = config->error_callback_dis; in max32_dma_config()
156 static int max32_dma_reload(const struct device *dev, uint32_t channel, uint32_t src, uint32_t dst, in max32_dma_reload() argument
163 if (channel >= cfg->channels) { in max32_dma_reload()
165 channel); in max32_dma_reload()
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| D | dma_sedi.c | 46 static void dma_handler(sedi_dma_t dma_device, int channel, int event_id, in dma_handler() argument
52 struct dma_config *config = &(data->dma_configs[channel]); in dma_handler()
59 channel, 0); in dma_handler()
62 channel, event_id); in dma_handler()
167 static int dma_sedi_apply_common_config(sedi_dma_t dev, uint32_t channel, in dma_sedi_apply_common_config() argument
180 sedi_dma_control(dev, channel, SEDI_CONFIG_DMA_DIRECTION, in dma_sedi_apply_common_config()
184 sedi_dma_control(dev, channel, SEDI_CONFIG_DMA_SR_MEM_TYPE, in dma_sedi_apply_common_config()
186 sedi_dma_control(dev, channel, SEDI_CONFIG_DMA_DT_MEM_TYPE, in dma_sedi_apply_common_config()
189 sedi_dma_control(dev, channel, SEDI_CONFIG_DMA_HS_DEVICE_ID, in dma_sedi_apply_common_config()
191 sedi_dma_control(dev, channel, SEDI_CONFIG_DMA_HS_POLARITY, in dma_sedi_apply_common_config()
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | dma.h | 191 uint32_t channel, int status);
315 typedef int (*dma_api_config)(const struct device *dev, uint32_t channel,
319 typedef int (*dma_api_reload)(const struct device *dev, uint32_t channel,
322 typedef int (*dma_api_reload)(const struct device *dev, uint32_t channel,
326 typedef int (*dma_api_start)(const struct device *dev, uint32_t channel);
328 typedef int (*dma_api_stop)(const struct device *dev, uint32_t channel);
330 typedef int (*dma_api_suspend)(const struct device *dev, uint32_t channel);
332 typedef int (*dma_api_resume)(const struct device *dev, uint32_t channel);
334 typedef int (*dma_api_get_status)(const struct device *dev, uint32_t channel,
353 int channel, void *filter_param);
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| D | pwm.h | 102 uint32_t channel; member
156 .channel = DT_PWMS_CHANNEL_BY_NAME(node_id, name), \
261 .channel = DT_PWMS_CHANNEL_BY_IDX(node_id, idx), \
392 uint32_t channel,
402 typedef int (*pwm_set_cycles_t)(const struct device *dev, uint32_t channel,
411 uint32_t channel, uint64_t *cycles);
419 uint32_t channel, pwm_flags_t flags,
427 typedef int (*pwm_enable_capture_t)(const struct device *dev, uint32_t channel);
434 uint32_t channel);
479 __syscall int pwm_set_cycles(const struct device *dev, uint32_t channel,
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.rv32m1 | 15 eight channels; each channel has its own level 1 interrupt to
28 bool "INTMUX channel 0"
30 Enable support for INTMUX channel 0.
33 bool "INTMUX channel 1"
35 Enable support for INTMUX channel 1.
38 bool "INTMUX channel 2"
40 Enable support for INTMUX channel 2.
43 bool "INTMUX channel 3"
45 Enable support for INTMUX channel 3.
48 bool "INTMUX channel 4"
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| /Zephyr-latest/drivers/mbox/ |
| D | mbox_nrfx_ipc.c | 53 uint32_t channel = event_idx; in mbox_dispatcher() local
55 if (!is_rx_channel_valid(dev, channel)) { in mbox_dispatcher()
59 if (!(data->enabled_mask & BIT(channel))) { in mbox_dispatcher()
63 if (data->cb[channel] != NULL) { in mbox_dispatcher()
64 data->cb[channel](dev, channel, data->user_data[channel], NULL); in mbox_dispatcher()
68 static int mbox_nrf_send(const struct device *dev, uint32_t channel, in mbox_nrf_send() argument
75 if (!is_tx_channel_valid(dev, channel)) { in mbox_nrf_send()
79 nrfx_ipc_signal(channel); in mbox_nrf_send()
84 static int mbox_nrf_register_callback(const struct device *dev, uint32_t channel, in mbox_nrf_register_callback() argument
89 if (channel >= IPC_CONF_NUM) { in mbox_nrf_register_callback()
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| /Zephyr-latest/include/zephyr/drivers/mfd/ |
| D | max31790.h | 20 #define MAX37190_REGISTER_FANCONFIGURATION(channel) (0x02 + channel) argument
21 #define MAX31790_REGISTER_FANDYNAMICS(channel) (0x08 + channel) argument
23 #define MAX37190_REGISTER_TACHCOUNTMSB(channel) (0x18 + 2 * channel) argument
24 #define MAX31790_REGISTER_PWMOUTTARGETDUTYCYCLEMSB(channel) (0x40 + 2 * channel) argument
25 #define MAX31790_REGISTER_TACHTARGETCOUNTMSB(channel) (0x50 + 2 * channel) argument
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| /Zephyr-latest/tests/drivers/timer/nrf_grtc_timer/src/ |
| D | main.c | 69 int32_t channel = z_nrf_grtc_timer_chan_alloc(); in ZTEST() local
71 TC_PRINT("Allocated GRTC channel %d\n", channel); in ZTEST()
72 if (channel < 0) { in ZTEST()
73 TC_PRINT("Failed to allocate GRTC channel, chan=%d\n", channel); in ZTEST()
79 err = z_nrf_grtc_timer_set(channel, test_ticks, timer_compare_interrupt_handler, in ZTEST()
84 z_nrf_grtc_timer_compare_read(channel, &compare_value); in ZTEST()
91 TC_PRINT("Compare event generated ?: %d\n", z_nrf_grtc_timer_compare_evt_check(channel)); in ZTEST()
93 z_nrf_grtc_timer_compare_evt_address_get(channel)); in ZTEST()
97 z_nrf_grtc_timer_chan_free(channel); in ZTEST()
106 int32_t channel = z_nrf_grtc_timer_chan_alloc(); in ZTEST() local
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| /Zephyr-latest/tests/drivers/audio/dmic_api/src/ |
| D | main.c | 57 .channel = {
82 cfg->streams[0].pcm_rate, cfg->channel.req_num_chan); in do_pdm_transfer()
91 zassert_equal(cfg->channel.act_num_chan, in do_pdm_transfer()
92 cfg->channel.req_num_chan, in do_pdm_transfer()
94 zassert_equal(cfg->channel.act_chan_map_lo, in do_pdm_transfer()
95 cfg->channel.req_chan_map_lo, in do_pdm_transfer()
97 zassert_equal(cfg->channel.act_chan_map_hi, in do_pdm_transfer()
98 cfg->channel.req_chan_map_hi, in do_pdm_transfer()
133 dmic_cfg.channel.req_num_chan = 1; in ZTEST()
134 dmic_cfg.channel.req_chan_map_lo = in ZTEST()
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| /Zephyr-latest/samples/subsys/input/input_dump/boards/ |
| D | esp32_devkitc_wroom_procpu.overlay | 14 channel-num = <9>;
15 channel-sens = <20>;
20 channel-num = <8>;
21 channel-sens = <20>;
26 channel-num = <6>;
27 channel-sens = <20>;
32 channel-num = <4>;
33 channel-sens = <20>;
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| D | esp32_devkitc_wrover_procpu.overlay | 14 channel-num = <9>;
15 channel-sens = <20>;
20 channel-num = <8>;
21 channel-sens = <20>;
26 channel-num = <6>;
27 channel-sens = <20>;
32 channel-num = <4>;
33 channel-sens = <20>;
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| D | esp32s2_saola.overlay | 14 channel-num = <9>;
15 channel-sens = <20>;
20 channel-num = <8>;
21 channel-sens = <20>;
26 channel-num = <6>;
27 channel-sens = <20>;
32 channel-num = <4>;
33 channel-sens = <20>;
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