54 		int channel = find_lsb_set(channels_event) - 1;                            \
57 		__ASSERT_NO_MSG(channel >= 0);                                             \
58 		dma_channel = &dev_data->channels[channel];                                \
61 		XMC_DMA_CH_ClearEventStatus(dma, channel, XMC_DMA_CH_##event_test);        \
63 			dma_channel->cb(dev, dma_channel->user_data, channel, (ret));      \
123 static int dma_xmc4xxx_config(const struct device *dev, uint32_t channel, struct dma_config *config)  in dma_xmc4xxx_config()  argument
131 	if (channel >= dev_data->ctx.dma_channels) {  in dma_xmc4xxx_config()
159 		if (dma != XMC_DMA0 || channel >= 2) {  in dma_xmc4xxx_config()
194 	if (XMC_DMA_CH_IsEnabled(dma, channel)) {  in dma_xmc4xxx_config()
199 	XMC_DMA_CH_ClearEventStatus(dma, channel, ALL_EVENTS);  in dma_xmc4xxx_config()
202 	dma->CH[channel].SAR = block->source_address;  in dma_xmc4xxx_config()
203 	dma->CH[channel].DAR = block->dest_address;  in dma_xmc4xxx_config()
204 	dma->CH[channel].LLP = 0;  in dma_xmc4xxx_config()
207 	dma->CH[channel].CTLH = block->block_size / config->source_data_size;  in dma_xmc4xxx_config()
210 	dma->CH[channel].CFGL = (config->channel_priority << GPDMA0_CH_CFGL_CH_PRIOR_Pos) |  in dma_xmc4xxx_config()
213 	dma->CH[channel].CTLL = config->dest_data_size / 2 << GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos |  in dma_xmc4xxx_config()
259 			dma->CH[channel].CFGH = (dlr_line_reg << GPDMA0_CH_CFGH_DEST_PER_Pos) | 4;  in dma_xmc4xxx_config()
260 			dma->CH[channel].CFGL &= ~BIT(GPDMA0_CH_CFGL_HS_SEL_DST_Pos);  in dma_xmc4xxx_config()
261 			dma->CH[channel].CTLL |= 1 << GPDMA0_CH_CTLL_TT_FC_Pos;  in dma_xmc4xxx_config()
265 			dma->CH[channel].CFGH = (dlr_line_reg << GPDMA0_CH_CFGH_SRC_PER_Pos) | 4;  in dma_xmc4xxx_config()
266 			dma->CH[channel].CFGL &= ~BIT(GPDMA0_CH_CFGL_HS_SEL_SRC_Pos);  in dma_xmc4xxx_config()
267 			dma->CH[channel].CTLL |= 2 << GPDMA0_CH_CTLL_TT_FC_Pos;  in dma_xmc4xxx_config()
272 		dma->CH[channel].CTLL |= BIT(GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos);  in dma_xmc4xxx_config()
274 		dma->CH[channel].SGR = (block->source_gather_interval & GPDMA0_CH_SGR_SGI_Msk) |  in dma_xmc4xxx_config()
279 		dma->CH[channel].CTLL |= BIT(GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos);  in dma_xmc4xxx_config()
281 		dma->CH[channel].DSR = (block->dest_scatter_interval & GPDMA0_CH_DSR_DSI_Msk) |  in dma_xmc4xxx_config()
285 	dev_data->channels[channel].cb = config->dma_callback;  in dma_xmc4xxx_config()
286 	dev_data->channels[channel].user_data = config->user_data;  in dma_xmc4xxx_config()
287 	dev_data->channels[channel].block_ts = block->block_size / config->source_data_size;  in dma_xmc4xxx_config()
288 	dev_data->channels[channel].source_data_size = config->source_data_size;  in dma_xmc4xxx_config()
289 	dev_data->channels[channel].dlr_line = dlr_line;  in dma_xmc4xxx_config()
291 	XMC_DMA_CH_DisableEvent(dma, channel, ALL_EVENTS);  in dma_xmc4xxx_config()
292 	XMC_DMA_CH_EnableEvent(dma, channel, XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);  in dma_xmc4xxx_config()
296 		XMC_DMA_CH_EnableEvent(dma, channel, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);  in dma_xmc4xxx_config()
300 		XMC_DMA_CH_EnableEvent(dma, channel, XMC_DMA_CH_EVENT_ERROR);  in dma_xmc4xxx_config()
303 	LOG_DBG("Configured channel %d for %08X to %08X (%u)", channel, block->source_address,  in dma_xmc4xxx_config()
309 static int dma_xmc4xxx_start(const struct device *dev, uint32_t channel)  in dma_xmc4xxx_start()  argument
313 	LOG_DBG("Starting channel %d", channel);  in dma_xmc4xxx_start()
314 	XMC_DMA_CH_Enable(dev_cfg->dma, channel);  in dma_xmc4xxx_start()
318 static int dma_xmc4xxx_stop(const struct device *dev, uint32_t channel)  in dma_xmc4xxx_stop()  argument
325 	dma_channel = &dev_data->channels[channel];  in dma_xmc4xxx_stop()
326 	XMC_DMA_CH_Suspend(dma, channel);  in dma_xmc4xxx_stop()
329 	while (XMC_DMA_CH_IsEnabled(dma, channel) &&  in dma_xmc4xxx_stop()
330 	      (dma->CH[channel].CFGL & GPDMA0_CH_CFGL_FIFO_EMPTY_Msk) == 0) {  in dma_xmc4xxx_stop()
341 	XMC_DMA_CH_Disable(dma, channel);  in dma_xmc4xxx_stop()
345 static int dma_xmc4xxx_reload(const struct device *dev, uint32_t channel, uint32_t src,  in dma_xmc4xxx_reload()  argument
354 	if (channel >= dev_data->ctx.dma_channels) {  in dma_xmc4xxx_reload()
359 	if (XMC_DMA_CH_IsEnabled(dma, channel)) {  in dma_xmc4xxx_reload()
364 	dma_channel = &dev_data->channels[channel];  in dma_xmc4xxx_reload()
373 	dma->CH[channel].SAR = src;  in dma_xmc4xxx_reload()
374 	dma->CH[channel].DAR = dst;  in dma_xmc4xxx_reload()
375 	dma->CH[channel].CTLH = block_ts;  in dma_xmc4xxx_reload()
380 static int dma_xmc4xxx_get_status(const struct device *dev, uint32_t channel,  in dma_xmc4xxx_get_status()  argument
388 	if (channel >= dev_data->ctx.dma_channels) {  in dma_xmc4xxx_get_status()
392 	dma_channel = &dev_data->channels[channel];  in dma_xmc4xxx_get_status()
394 	stat->busy = XMC_DMA_CH_IsEnabled(dma, channel);  in dma_xmc4xxx_get_status()
396 	stat->pending_length  = dma_channel->block_ts - XMC_DMA_CH_GetTransferredData(dma, channel);  in dma_xmc4xxx_get_status()
404 static bool dma_xmc4xxx_chan_filter(const struct device *dev, int channel, void *filter_param)  in dma_xmc4xxx_chan_filter()  argument
414 	if (channel == requested_channel) {  in dma_xmc4xxx_chan_filter()
421 static int dma_xmc4xxx_suspend(const struct device *dev, uint32_t channel)  in dma_xmc4xxx_suspend()  argument
427 	if (channel >= dev_data->ctx.dma_channels) {  in dma_xmc4xxx_suspend()
432 	XMC_DMA_CH_Suspend(dma, channel);  in dma_xmc4xxx_suspend()
436 static int dma_xmc4xxx_resume(const struct device *dev, uint32_t channel)  in dma_xmc4xxx_resume()  argument
442 	if (channel >= dev_data->ctx.dma_channels) {  in dma_xmc4xxx_resume()
447 	XMC_DMA_CH_Resume(dma, channel);  in dma_xmc4xxx_resume()