57 static void dma_si32_isr_handler(const uint8_t channel)  in dma_si32_isr_handler()  argument
59 	const struct SI32_DMADESC_A_Struct *channel_descriptor = &channel_descriptors[channel];  in dma_si32_isr_handler()
60 	const dma_callback_t cb = dma_si32_data.channel_data[channel].callback;  in dma_si32_isr_handler()
61 	void *user_data = dma_si32_data.channel_data[channel].callback_user_data;  in dma_si32_isr_handler()
64 	LOG_INF("Channel %" PRIu8 " ISR fired", channel);  in dma_si32_isr_handler()
66 	irq_disable(DMACH0_IRQn + channel);  in dma_si32_isr_handler()
69 		LOG_ERR("Bus error on channel %" PRIu8, channel);  in dma_si32_isr_handler()
77 		__ASSERT((SI32_DMACTRL_0->CHENSET.U32 & BIT(channel)) == 0,  in dma_si32_isr_handler()
85 	cb(DEVICE_DT_INST_GET(0), user_data, channel, result);  in dma_si32_isr_handler()
88 #define DMA_SI32_IRQ_CONNECT(channel)                                                              \  argument
90 		IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, channel, irq),                                   \
91 			    DT_INST_IRQ_BY_IDX(0, channel, priority), dma_si32_isr_handler,        \
92 			    channel, 0);                                                           \
128 static int dma_si32_config(const struct device *dev, uint32_t channel, struct dma_config *cfg)  in dma_si32_config()  argument
137 	LOG_INF("Configuring channel %" PRIu8, channel);  in dma_si32_config()
139 	if (channel >= CHANNEL_COUNT) {  in dma_si32_config()
140 		LOG_ERR("Invalid channel (id %" PRIu32 ", have %d)", channel, CHANNEL_COUNT);  in dma_si32_config()
147 	if (SI32_DMACTRL_A_is_channel_enabled(SI32_DMACTRL_0, channel)) {  in dma_si32_config()
152 	channel_descriptor = &channel_descriptors[channel];  in dma_si32_config()
224 	channel_data = &dma_si32_data.channel_data[channel];  in dma_si32_config()
293 		SI32_DMACTRL_A_disable_data_request(SI32_DMACTRL_0, channel);  in dma_si32_config()
302 		SI32_DMACTRL_A_enable_data_request(SI32_DMACTRL_0, channel);  in dma_si32_config()
347 static int dma_si32_start(const struct device *dev, const uint32_t channel)  in dma_si32_start()  argument
351 	struct SI32_DMADESC_A_Struct *channel_desc = &channel_descriptors[channel];  in dma_si32_start()
354 	LOG_INF("Starting channel %" PRIu8, channel);  in dma_si32_start()
356 	if (channel >= CHANNEL_COUNT) {  in dma_si32_start()
357 		LOG_ERR("Invalid channel (id %" PRIu32 ", have %d)", channel, CHANNEL_COUNT);  in dma_si32_start()
361 	channel_data = &dma_si32_data.channel_data[channel];  in dma_si32_start()
371 	__ASSERT(SI32_DMACTRL_A_is_primary_selected(SI32_DMACTRL_0, channel),  in dma_si32_start()
374 	__ASSERT(SI32_DMACTRL_0->CHSTATUS.U32 & BIT(channel),  in dma_si32_start()
383 	irq_enable(DMACH0_IRQn + channel);  in dma_si32_start()
385 	SI32_DMACTRL_A_enable_channel(SI32_DMACTRL_0, channel);  in dma_si32_start()
390 	if (dma_si32_data.channel_data[channel].memory_to_memory) {  in dma_si32_start()
391 		__ASSERT((SI32_DMACTRL_0->CHREQMSET.U32 & BIT(channel)),  in dma_si32_start()
393 		SI32_DMACTRL_A_generate_software_request(SI32_DMACTRL_0, channel);  in dma_si32_start()
395 		__ASSERT(!(SI32_DMACTRL_0->CHREQMSET.U32 & BIT(channel)),  in dma_si32_start()
402 static int dma_si32_stop(const struct device *dev, const uint32_t channel)  in dma_si32_stop()  argument
406 	if (channel >= CHANNEL_COUNT) {  in dma_si32_stop()
407 		LOG_ERR("Invalid channel (id %" PRIu32 ", have %d)", channel, CHANNEL_COUNT);  in dma_si32_stop()
411 	irq_disable(DMACH0_IRQn + channel);  in dma_si32_stop()
413 	channel_descriptors[channel].CONFIG.TMD = 0; /* Stop the DMA channel. */  in dma_si32_stop()
415 	SI32_DMACTRL_A_disable_channel(SI32_DMACTRL_0, channel);  in dma_si32_stop()