Lines Matching refs:channel
37 uint32_t channel; in dw_dma_isr() local
61 channel = find_lsb_set(status_block) - 1; in dw_dma_isr()
62 status_block &= ~(1 << channel); in dw_dma_isr()
63 chan_data = &dev_data->chan[channel]; in dw_dma_isr()
67 channel); in dw_dma_isr()
75 channel, DMA_STATUS_BLOCK); in dw_dma_isr()
80 channel = find_lsb_set(status_tfr) - 1; in dw_dma_isr()
81 status_tfr &= ~(1 << channel); in dw_dma_isr()
82 chan_data = &dev_data->chan[channel]; in dw_dma_isr()
92 channel); in dw_dma_isr()
95 channel, DMA_STATUS_COMPLETE); in dw_dma_isr()
124 int dw_dma_config(const struct device *dev, uint32_t channel, in dw_dma_config() argument
138 if (channel >= DW_CHAN_COUNT) { in dw_dma_config()
139 LOG_ERR("%s: invalid dma channel %d", dev->name, channel); in dw_dma_config()
144 struct dw_dma_chan_data *chan_data = &dev_data->chan[channel]; in dw_dma_config()
148 channel, chan_data->state); in dw_dma_config()
153 LOG_DBG("%s: channel %d config", dev->name, channel); in dw_dma_config()
163 LOG_ERR("%s: channel %d 'invalid source_data_size' value %d", dev->name, channel, in dw_dma_config()
172 dev->name, channel); in dw_dma_config()
179 LOG_DBG("%s: channel %d m_size=%d", dev->name, channel, msize); in dw_dma_config()
188 chan_data->lli = &dev_data->lli_pool[channel][0]; /* TODO allocate here */ in dw_dma_config()
229 LOG_ERR("%s: channel %d invalid src width %d", dev->name, channel, in dw_dma_config()
261 LOG_ERR("%s: channel %d invalid dest width %d", dev->name, channel, in dw_dma_config()
337 LOG_ERR("%s: channel %d invalid direction %d", dev->name, channel, in dw_dma_config()
353 LOG_ERR("%s: channel %d block size too big %d", dev->name, channel, in dw_dma_config()
360 lli_desc->ctrl_hi |= DW_CTLH_CLASS(dev_data->channel_data->chan[channel].class) | in dw_dma_config()
416 dw_write(dev_cfg->base, DW_MASK_BLOCK, DW_CHAN_UNMASK(channel)); in dw_dma_config()
420 dw_write(dev_cfg->base, DW_MASK_TFR, DW_CHAN_UNMASK(channel)); in dw_dma_config()
423 dw_write(dev_cfg->base, DW_MASK_ERR, DW_CHAN_UNMASK(channel)); in dw_dma_config()
428 dw_write(dev_cfg->base, DW_CLEAR_TFR, 0x1 << channel); in dw_dma_config()
429 dw_write(dev_cfg->base, DW_CLEAR_BLOCK, 0x1 << channel); in dw_dma_config()
430 dw_write(dev_cfg->base, DW_CLEAR_SRC_TRAN, 0x1 << channel); in dw_dma_config()
431 dw_write(dev_cfg->base, DW_CLEAR_DST_TRAN, 0x1 << channel); in dw_dma_config()
432 dw_write(dev_cfg->base, DW_CLEAR_ERR, 0x1 << channel); in dw_dma_config()
439 bool dw_dma_is_enabled(const struct device *dev, uint32_t channel) in dw_dma_is_enabled() argument
443 return dw_read(dev_cfg->base, DW_DMA_CHAN_EN) & DW_CHAN(channel); in dw_dma_is_enabled()
446 int dw_dma_start(const struct device *dev, uint32_t channel) in dw_dma_start() argument
453 if (channel >= DW_CHAN_COUNT) { in dw_dma_start()
458 if (dw_dma_is_enabled(dev, channel)) { in dw_dma_start()
462 struct dw_dma_chan_data *chan_data = &dev_data->chan[channel]; in dw_dma_start()
466 LOG_ERR("%s: channel %d not ready ena 0x%x status 0x%x", dev->name, channel, in dw_dma_start()
474 LOG_ERR("%s: channel %d invalid stream", dev->name, channel); in dw_dma_start()
479 LOG_INF("%s: channel %d start", dev->name, channel); in dw_dma_start()
493 dw_write(dev_cfg->base, DW_LLP(channel), llp); in dw_dma_start()
495 lli->ctrl_lo, masked_ctrl_lo, dw_read(dev_cfg->base, DW_LLP(channel))); in dw_dma_start()
500 dw_write(dev_cfg->base, DW_SAR(channel), (uint32_t)(lli->sar & DW_ADDR_MASK_32)); in dw_dma_start()
501 dw_write(dev_cfg->base, DW_SAR_HI(channel), (uint32_t)(lli->sar >> DW_ADDR_RIGHT_SHIFT)); in dw_dma_start()
502 dw_write(dev_cfg->base, DW_DAR(channel), (uint32_t)(lli->dar & DW_ADDR_MASK_32)); in dw_dma_start()
503 dw_write(dev_cfg->base, DW_DAR_HI(channel), (uint32_t)(lli->dar >> DW_ADDR_RIGHT_SHIFT)); in dw_dma_start()
505 dw_write(dev_cfg->base, DW_SAR(channel), lli->sar); in dw_dma_start()
506 dw_write(dev_cfg->base, DW_DAR(channel), lli->dar); in dw_dma_start()
510 dw_write(dev_cfg->base, DW_CTRL_LOW(channel), lli->ctrl_lo); in dw_dma_start()
511 dw_write(dev_cfg->base, DW_CTRL_HIGH(channel), lli->ctrl_hi); in dw_dma_start()
514 dw_write(dev_cfg->base, DW_CFG_LOW(channel), chan_data->cfg_lo); in dw_dma_start()
515 dw_write(dev_cfg->base, DW_CFG_HIGH(channel), chan_data->cfg_hi); in dw_dma_start()
520 chan_data->cfg_hi, dw_read(dev_cfg->base, DW_LLP(channel)) in dw_dma_start()
525 chan_data->cfg_hi, dw_read(dev_cfg->base, DW_LLP(channel)) in dw_dma_start()
534 dw_write(dev_cfg->base, DW_DSR(channel), in dw_dma_start()
542 dw_write(dev_cfg->base, DW_DMA_CHAN_EN, DW_CHAN_UNMASK(channel)); in dw_dma_start()
549 int dw_dma_stop(const struct device *dev, uint32_t channel) in dw_dma_stop() argument
553 struct dw_dma_chan_data *chan_data = &dev_data->chan[channel]; in dw_dma_stop()
557 if (channel >= DW_CHAN_COUNT) { in dw_dma_stop()
572 if (!dw_dma_is_enabled(dev, channel) && chan_data->state != DW_DMA_SUSPENDED) { in dw_dma_stop()
582 LOG_INF("%s: channel %d stop", dev->name, channel); in dw_dma_stop()
595 dw_write(dev_cfg->base, DW_CFG_LOW(channel), in dw_dma_stop()
599 bool fifo_empty = WAIT_FOR(dw_read(dev_cfg->base, DW_CFG_LOW(channel)) & DW_CFGL_FIFO_EMPTY, in dw_dma_stop()
602 LOG_WRN("%s: channel %d drain time out", dev->name, channel); in dw_dma_stop()
612 dw_write(dev_cfg->base, DW_DMA_CHAN_EN, DW_CHAN_MASK(channel)); in dw_dma_stop()
615 bool is_disabled = WAIT_FOR(!(dw_read(dev_cfg->base, DW_DMA_CHAN_EN) & DW_CHAN(channel)), in dw_dma_stop()
618 LOG_ERR("%s: channel %d disable timeout", dev->name, channel); in dw_dma_stop()
634 int dw_dma_resume(const struct device *dev, uint32_t channel) in dw_dma_resume() argument
641 if (channel >= DW_CHAN_COUNT) { in dw_dma_resume()
646 struct dw_dma_chan_data *chan_data = &dev_data->chan[channel]; in dw_dma_resume()
654 LOG_DBG("%s: channel %d resume", dev->name, channel); in dw_dma_resume()
656 dw_write(dev_cfg->base, DW_CFG_LOW(channel), chan_data->cfg_lo); in dw_dma_resume()
665 int dw_dma_suspend(const struct device *dev, uint32_t channel) in dw_dma_suspend() argument
672 if (channel >= DW_CHAN_COUNT) { in dw_dma_suspend()
677 struct dw_dma_chan_data *chan_data = &dev_data->chan[channel]; in dw_dma_suspend()
686 LOG_DBG("%s: channel %d suspend", dev->name, channel); in dw_dma_suspend()
688 dw_write(dev_cfg->base, DW_CFG_LOW(channel), in dw_dma_suspend()
760 uint32_t channel) in dw_dma_avail_data_size() argument
763 int32_t write_ptr = dw_read(base, DW_DAR(channel)); in dw_dma_avail_data_size()
781 LOG_DBG("%s: channel %d: size is 0!", dev->name, channel); in dw_dma_avail_data_size()
785 LOG_DBG("%s: channel %d: DAR %x reader 0x%x free 0x%x avail 0x%x", dev->name, channel, in dw_dma_avail_data_size()
793 uint32_t channel) in dw_dma_free_data_size() argument
795 int32_t read_ptr = dw_read(base, DW_SAR(channel)); in dw_dma_free_data_size()
813 LOG_DBG("%s: channel %d: size is 0!", dev->name, channel); in dw_dma_free_data_size()
817 LOG_DBG("%s: channel %d: SAR %x writer 0x%x free 0x%x avail 0x%x", dev->name, channel, in dw_dma_free_data_size()
823 int dw_dma_get_status(const struct device *dev, uint32_t channel, in dw_dma_get_status() argument
830 if (channel >= DW_CHAN_COUNT) { in dw_dma_get_status()
834 chan_data = &dev_data->chan[channel]; in dw_dma_get_status()
839 channel); in dw_dma_get_status()
843 stat->free = dw_dma_free_data_size(dev, dev_cfg->base, chan_data, channel); in dw_dma_get_status()
847 if (!(dw_read(dev_cfg->base, DW_DMA_CHAN_EN) & DW_CHAN(channel))) { in dw_dma_get_status()