Home
last modified time | relevance | path

Searched refs:cacheable (Results 1 – 22 of 22) sorted by relevance

/Zephyr-latest/doc/kernel/memory_management/
Dshared_multi_heap.rst8 attributes (cacheable, non-cacheable, etc...).
31 // Fill the struct with the data for cacheable memory
41 // Add another cacheable region
50 // Add a non-cacheable region
69 // Allocate 4K from cacheable memory
72 // Allocate 4K from non-cacheable memory
/Zephyr-latest/arch/arm/core/mmu/
Darm_mmu_priv.h91 uint32_t cacheable : 1; member
128 uint32_t cacheable : 1; member
139 uint32_t cacheable : 1; member
192 uint32_t cacheable : 1; member
Darm_mmu.c294 perms_attrs.cacheable = 0; in arm_mmu_convert_attr_flags()
304 perms_attrs.cacheable = 0; in arm_mmu_convert_attr_flags()
339 perms_attrs.cacheable = ARM_MMU_C_CACHE_ATTRS_WB_WA; in arm_mmu_convert_attr_flags()
342 perms_attrs.cacheable = ARM_MMU_C_CACHE_ATTRS_WT_nWA; in arm_mmu_convert_attr_flags()
345 perms_attrs.cacheable = ARM_MMU_C_CACHE_ATTRS_WB_nWA; in arm_mmu_convert_attr_flags()
422 l1_page_table.entries[l1_index].l1_section_1m.cacheable = perms_attrs.cacheable; in arm_mmu_l1_map_section()
485 perms_attrs.cacheable = l1_page_table.entries[l1_index].l1_section_1m.cacheable; in arm_mmu_remap_l1_section_to_l2_table()
660 l2_page_table->entries[l2_index].l2_page_4k.cacheable = perms_attrs.cacheable; in arm_mmu_l2_map_page()
/Zephyr-latest/boards/nxp/mimxrt1060_evk/
Dmimxrt1060_evk_mimxrt1062_hyperflash.dts22 ahb-cacheable;
/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk_mimxrt1052_hyperflash.dts24 ahb-cacheable;
/Zephyr-latest/doc/services/mem_mgmt/
Dindex.rst14 For example, to mark a memory region in the devicetree as non-volatile, cacheable,
153 // Allocate 0x100 bytes of cacheable memory from `mem_cacheable`
156 // Allocate 0x200 bytes of non-cacheable memory aligned to 32 bytes
160 // Allocate 0x100 bytes of cacheable and dma-able memory from `mem_cacheable_dma`
/Zephyr-latest/lib/heap/
DKconfig145 different capabilities / attributes (cacheable, non-cacheable,
/Zephyr-latest/boards/nxp/frdm_rw612/
Dfrdm_rw612_common.dtsi74 ahb-cacheable;
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dfrdm_mcxn947.dtsi180 ahb-cacheable;
/Zephyr-latest/boards/nxp/rd_rw612_bga/
Drd_rw612_bga.dtsi129 ahb-cacheable;
/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6.dts183 ahb-cacheable;
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt1010.dtsi110 ahb-cacheable;
Dnxp_rt10xx.dtsi130 ahb-cacheable;
142 ahb-cacheable;
Dnxp_rt7xx_cm33_cpu0.dtsi83 * 2MB non-cacheable data for NPU/GPU/Display etc.
/Zephyr-latest/arch/xtensa/
DKconfig263 Default memory type for memory regions: non-cacheable memory,
/Zephyr-latest/boards/nxp/mimxrt595_evk/
Dmimxrt595_evk_mimxrt595s_cm33.dts439 ahb-cacheable;
/Zephyr-latest/doc/hardware/cache/
Dguide.rst130 cacheable memory, the cache line. Data cache lines are typically 16 to 128
/Zephyr-latest/doc/hardware/arch/
Darm_cortex_m.rst63 |Support for non-cacheable regions| | N | N |…
462 For example, to define a new non-cacheable memory region in devicetree:
486 * a ``nocache`` region to allow for a non-cacheable SRAM area, when :kconfig:option:`CONFIG_NOCACHE…
/Zephyr-latest/arch/xtensa/core/
DREADME_MMU.txt245 cacheable, then the hardware TLB refill process will be downstream of
/Zephyr-latest/doc/releases/
Drelease-notes-3.7.rst1252 * Added support to identify if DMA buffers are in data cache or non-cacheable memory.
Drelease-notes-1.14.rst617 * Support non-cacheable memory sections
Drelease-notes-3.3.rst894 - Support DMA operation on SOCs that do not support non-cacheable memory,