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Searched refs:STM32_SRC_PLL_Q (Results 1 – 25 of 31) sorted by relevance

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/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32f4_clock.h35 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) macro
36 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
Dstm32wb_clock.h37 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) macro
38 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
Dstm32wl_clock.h38 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) macro
39 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
Dstm32u0_clock.h36 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) macro
37 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
Dstm32g4_clock.h38 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) macro
39 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
Dstm32g0_clock.h35 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) macro
36 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
Dstm32l4_clock.h36 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) macro
37 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
Dstm32f7_clock.h36 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) macro
37 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
/Zephyr-latest/dts/arm/st/f4/
Dstm32f469.dtsi21 <&rcc STM32_SRC_PLL_Q CLK48M_SEL(0)>;
Dstm32f446.dtsi84 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
97 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
/Zephyr-latest/samples/subsys/usb/shell/
Dnucleo_f413zh_dwc2.overlay17 <&rcc STM32_SRC_PLL_Q NO_SEL>;
/Zephyr-latest/boards/others/candlelightfd/
Dcandlelightfd_stm32g0b1xx_dual.dts25 <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>;
Dcandlelightfd.dtsi78 <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>;
/Zephyr-latest/samples/subsys/usb/cdc_acm/
Dnucleo_f413zh_dwc2.overlay17 <&rcc STM32_SRC_PLL_Q NO_SEL>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Df4_sdmmc48_pll.overlay10 /* clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;*/
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_common.c201 #if defined(STM32_SRC_PLL_Q) in enabled_clock()
202 case STM32_SRC_PLL_Q: in enabled_clock()
412 #if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED in stm32_clock_control_get_subsys_rate()
413 case STM32_SRC_PLL_Q: in stm32_clock_control_get_subsys_rate()
599 #if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED in set_up_plls()
/Zephyr-latest/dts/arm/st/f7/
Dstm32f722.dtsi39 <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
Dstm32f765.dtsi88 <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
/Zephyr-latest/boards/st/nucleo_g0b1re/
Dnucleo_g0b1re.dts183 <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>;
191 <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>;
/Zephyr-latest/boards/makerbase/mks_canable_v20/
Dmks_canable_v20.dts85 <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>;
/Zephyr-latest/boards/weact/usb2canfdv1/
Dusb2canfdv1.dts82 <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>;
/Zephyr-latest/boards/adi/sdp_k1/
Dadi_sdp_k1.dts106 <&rcc STM32_SRC_PLL_Q NO_SEL>;
/Zephyr-latest/boards/st/stm32f469i_disco/
Dstm32f469i_disco.dts130 <&rcc STM32_SRC_PLL_Q CLK48M_SEL(0)>;
/Zephyr-latest/boards/weact/stm32g431_core/
Dweact_stm32g431_core.dts184 <&rcc STM32_SRC_PLL_Q CLK48_SEL(2)>;
/Zephyr-latest/boards/st/nucleo_l476rg/
Dnucleo_l476rg.dts201 <&rcc STM32_SRC_PLL_Q CLK48_SEL(2)>;

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