1/*
2 * Copyright (c) 2024 Sean Nyekjaer <sean@geanix.com>
3 *
4 *  SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/g0/stm32g0b1Xb.dtsi>
8#include <st/g0/stm32g0b1r(b-c-e)tx-pinctrl.dtsi>
9
10/ {
11	chosen {
12		zephyr,sram = &sram0;
13		zephyr,flash = &flash0;
14		zephyr,code-partition = &slot0_partition;
15		zephyr,canbus = &fdcan1;
16	};
17
18	aliases {
19		led0 = &led_rx;
20		led1 = &led_tx;
21	};
22
23	leds {
24		compatible = "gpio-leds";
25		led_rx: led_rx {
26			gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
27			label = "LED RX";
28		};
29		led_tx: led_tx {
30			gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
31			label = "LED TX";
32		};
33	};
34
35	transceiver0: can-phy0 {
36		compatible = "nxp,tja1051", "can-transceiver-gpio";
37		enable-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
38		max-bitrate = <5000000>;
39		#phy-cells = <0>;
40	};
41};
42
43&clk_hse {
44	status = "okay";
45	clock-frequency = <DT_FREQ_M(8)>;
46};
47
48&clk_hsi48 {
49	status = "okay";
50	crs-usb-sof;
51};
52
53&pll {
54	div-m = <1>;
55	mul-n = <30>;
56	div-p = <2>;
57	div-q = <3>;
58	div-r = <4>;
59	clocks = <&clk_hse>;
60	status = "okay";
61};
62
63&rcc {
64	clocks = <&pll>;
65	clock-frequency = <DT_FREQ_M(60)>;
66	ahb-prescaler = <1>;
67	apb1-prescaler = <1>;
68};
69
70zephyr_udc0: &usb {
71	pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
72	pinctrl-names = "default";
73	status = "okay";
74};
75
76&fdcan1 {
77	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>,
78		 <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>;
79	pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>;
80	pinctrl-names = "default";
81	phys = <&transceiver0>;
82	status = "okay";
83};
84
85&flash0 {
86	partitions {
87		compatible = "fixed-partitions";
88		#address-cells = <1>;
89		#size-cells = <1>;
90
91		boot_partition: partition@0 {
92			label = "mcuboot";
93			reg = <0x00000000 DT_SIZE_K(48)>;
94			read-only;
95		};
96		slot0_partition: partition@c000 {
97			label = "image-0";
98			reg = <0x0000c000 DT_SIZE_K(80)>;
99		};
100	};
101};
102