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Searched refs:STM32_SRC_HSI (Results 1 – 25 of 40) sorted by relevance

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/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32f1_clock.h26 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) macro
27 #define STM32_SRC_HSE (STM32_SRC_HSI + 1)
Dstm32l0_clock.h29 #define STM32_SRC_HSI (STM32_SRC_HSE + 1) macro
30 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
Dstm32f0_clock.h25 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) macro
26 #define STM32_SRC_HSI14 (STM32_SRC_HSI + 1)
Dstm32f4_clock.h31 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) macro
32 #define STM32_SRC_HSE (STM32_SRC_HSI + 1)
Dstm32c0_clock.h27 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) macro
28 #define STM32_SRC_HSE (STM32_SRC_HSI + 1)
Dstm32wb_clock.h29 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) macro
30 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
Dstm32wl_clock.h31 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) macro
32 #define STM32_SRC_MSI (STM32_SRC_HSI + 1)
Dstm32u0_clock.h28 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) macro
29 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
Dstm32f3_clock.h27 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) macro
30 #define STM32_SRC_PCLK (STM32_SRC_HSI + 1)
Dstm32g4_clock.h30 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) macro
31 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
Dstm32g0_clock.h27 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) macro
28 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
Dstm32l1_clock.h27 #define STM32_SRC_HSI (STM32_SRC_HSE + 1) macro
Dstm32l4_clock.h29 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) macro
30 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
Dstm32f7_clock.h32 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) macro
33 #define STM32_SRC_HSE (STM32_SRC_HSI + 1)
Dstm32h5_clock.h21 #define STM32_SRC_HSI (STM32_SRC_CSI + 1) macro
22 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
Dstm32n6_clock.h19 #define STM32_SRC_HSI (STM32_SRC_HSE + 1) macro
20 #define STM32_SRC_MSI (STM32_SRC_HSI + 1)
/Zephyr-latest/samples/boards/st/mco/boards/
Dnucleo_f446ze.overlay14 /* clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>; */
Dnucleo_f411re.overlay19 clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>;
/Zephyr-latest/samples/boards/st/power_mgmt/serial_wakeup/boards/
Dnucleo_h563zi.overlay10 <&rcc STM32_SRC_HSI USART3_SEL(3)>;
Dstm32l562e_dk.overlay44 <&rcc STM32_SRC_HSI USART1_SEL(2)>;
Dnucleo_wb55rg.overlay19 <&rcc STM32_SRC_HSI USART1_SEL(2)>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Df0_i2c1_hsi.overlay68 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
Df3_i2c1_hsi.overlay68 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay69 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
Dg4_i2c1_hsi_adc1_pllp.overlay65 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;

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