Home
last modified time | relevance | path

Searched refs:STM32_PLL_ENABLED (Results 1 – 14 of 14) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32g4.c19 #if defined(STM32_PLL_ENABLED)
Dclock_stm32g0_u0.c20 #if defined(STM32_PLL_ENABLED)
Dclock_stm32l4_l5_wb_wl.c20 #if defined(STM32_PLL_ENABLED)
Dclock_stm32l0_l1.c19 #if defined(STM32_PLL_ENABLED)
Dclock_stm32f1.c24 #if defined(STM32_PLL_ENABLED)
Dclock_stm32f0_f3.c18 #if defined(STM32_PLL_ENABLED)
Dclock_stm32_ll_common.h49 #if defined(STM32_PLL_ENABLED)
Dclock_stm32f2_f4_f7.c19 #if defined(STM32_PLL_ENABLED)
Dclock_stm32_ll_u5.c296 #if defined(STM32_PLL_ENABLED) in stm32_clock_control_get_subsys_rate()
433 #if defined(STM32_PLL_ENABLED)
512 #if defined(STM32_PLL_ENABLED) || defined(STM32_PLL2_ENABLED) || \ in set_up_plls()
518 #if defined(STM32_PLL_ENABLED) in set_up_plls()
Dclock_stm32_ll_common.c191 if (!IS_ENABLED(STM32_PLL_ENABLED)) { in enabled_clock()
558 #if defined(STM32_PLL_ENABLED) in set_up_plls()
600 #if defined(STM32_PLL_ENABLED) in set_up_plls()
Dclock_stm32_ll_h5.c281 #if defined(STM32_PLL_ENABLED) in stm32_clock_control_get_subsys_rate()
430 #if defined(STM32_PLL_ENABLED) || defined(STM32_PLL2_ENABLED) || \ in set_up_plls()
437 #if defined(STM32_PLL_ENABLED) in set_up_plls()
Dclock_stm32_ll_wba.c225 #if defined(STM32_PLL_ENABLED) in stm32_clock_control_get_subsys_rate()
383 #if defined(STM32_PLL_ENABLED) in set_up_plls()
Dclock_stm32_ll_h7.c234 #if defined(STM32_PLL_ENABLED) in get_hclk_frequency()
553 #if defined(STM32_PLL_ENABLED)
766 #if defined(STM32_PLL_ENABLED) || defined(STM32_PLL2_ENABLED) || defined(STM32_PLL3_ENABLED)
830 #if defined(STM32_PLL_ENABLED)
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h160 #define STM32_PLL_ENABLED 1 macro
232 #define STM32_PLL_ENABLED 1 macro
239 #define STM32_PLL_ENABLED 1 macro
244 #define STM32_PLL_ENABLED 1 macro