Searched refs:S1 (Results 1 – 14 of 14) sorted by relevance
3 ARM V2M Musca-S110 on the V2M Musca-S1 board. It provides support for the Musca-S1 ARM Cortex-M3320 :alt: ARM V2M Musca-S122 More information about the board can be found at the `V2M Musca-S1 Website`_.27 ARM V2M MUSCA-S1 provides the following hardware components:94 See the `V2M Musca-S1 Website`_ for a complete list of V2M Musca-S1 board103 Musca-S1 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs.164 The ARM V2M Musca-S1 board's GPIO controller is responsible for pin-muxing,168 Mapping from the ARM V2M Musca-S1 Board pins to GPIO controller pins:202 For more details please refer to `Musca-S1 Technical Reference Manual (TRM)`_.[all …]
68 I: N -> S1: T1 prio 569 I: 0 -> S1: T1 prio 577 I: N -> S1: T1 prio 578 I: 1 -> S1: T1 prio 5112 I: N -> S1: T1 prio 5113 I: 6 -> S1: T1 prio 5146 I: N -> S1: T1 prio 5147 I: 0 -> S1: T1 prio 5155 I: N -> S1: T1 prio 5156 I: 1 -> S1: T1 prio 5[all …]
43 statement S1,S2;47 if@p1 ((E == NULL && ...) || ...) S1 else S256 statement S1,S2,S3,S4;64 ... when != if (...) S1 else S2117 statement S1,S2,S3,S4;125 ... when != if (...) S1 else S2177 statement S1,S2,S3,S4;185 ... when != if (...) S1 else S2239 statement S1,S2;243 if@p1 ((E == NULL && ...) || ...) S1 else S2[all …]
68 statement S1,S2;74 when != if@pif (...) S1
56 enum demo_state { S0, S1, S2 };60 [S1] = SMF_CREATE_STATE(s1_entry, s1_run, s1_exit, NULL, NULL),66 enum demo_state { S0, S1, S2 };70 [S1] = SMF_CREATE_STATE(s1_entry, s1_run, s1_exit, parent_s12, NULL),78 enum demo_state { S0, S1, S2 };85 [S1] = SMF_CREATE_STATE(s1_entry, s1_run, s1_exit, demo_states[S0], NULL),185 enum demo_state { S0, S1, S2 };202 smf_set_state(SMF_CTX(&s_obj), &demo_states[S1]);209 /* State S1 */232 /* State S1 does not have an entry action */[all …]
20 ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-S1
162 ascending priority ``S1``, ``MS2``, ``MS1``, and ``T1`` (the highest priority); two listeners,163 ``L1`` and ``L2``; and channel A. Supposing ``L1``, ``L2``, ``MS1``, ``MS2``, and ``S1`` observer182 ZBUS_OBSERVERS(L1, L2, MS1, MS2, S1), /* observers */197 ZBus VDED execution detail for priority T1 > MS1 > MS2 > S1.203 execution. The scenario considers the following priorities: T1 > MS1 > MS2 > S1. T1 has the highest207 .. list-table:: VDED execution steps in detail for priority T1 > MS1 > MS2 > S1.230 - The VDED pushes the notification message to the queue of S1. Notice the thread gets ready to242 - MS2 finishes execution. The S1 leaves the pending state and starts executing.245 - The S1 leaves the pending state since channel A is not locked. It gets in the CPU again and250 - S1 finishes its workload.[all …]
33 S1 DIP switches are shipped in Open Alliance SPI mode. The current Zephyr35 so the S1 DIP switches must be set as ``SPI_CFG0 OFF and SPI_CFG1 OFF``.36 An inconsistent S1 DIP switches configuration will halt the boot.
26 S1 = 9 variable in RegNum
267 .. note:: When west process started press Reset button ``S1`` and do not release it285 #. If Dediprog can't detect the onboard flash, press the board's ``S1`` Reset button and try again.
34 label = "Push button switch 1 (S1)";
248 | AIN1 | S1 |338 | THERM1 | S1 |
18 - S1 - On/Off (MX7_ONOFF signal)
24 - S1 - Reset Button (POR_B signal)
