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Searched refs:REG_WRITE (Results 1 – 14 of 14) sorted by relevance

/Zephyr-latest/drivers/interrupt_controller/
Dintc_wkpu_nxp_s32.c35 #define REG_WRITE(r, v) sys_write32((v), config->base + (r)) macro
65 REG_WRITE(WKPU_WISR(irq / 32U), REG_READ(WKPU_WISR(irq / 32U)) | irq_mask); in wkpu_nxp_s32_interrupt_handler()
125 REG_WRITE(WKPU_WIREER(reg_idx), reg_val); in wkpu_nxp_s32_enable_interrupt()
133 REG_WRITE(WKPU_WIFEER(reg_idx), reg_val); in wkpu_nxp_s32_enable_interrupt()
136 REG_WRITE(WKPU_WISR(reg_idx), REG_READ(WKPU_WISR(reg_idx)) | mask); in wkpu_nxp_s32_enable_interrupt()
137 REG_WRITE(WKPU_IRER(reg_idx), REG_READ(WKPU_IRER(reg_idx)) | mask); in wkpu_nxp_s32_enable_interrupt()
149 REG_WRITE(WKPU_WIREER(reg_idx), REG_READ(WKPU_WIREER(reg_idx)) & ~mask); in wkpu_nxp_s32_disable_interrupt()
150 REG_WRITE(WKPU_WIFEER(reg_idx), REG_READ(WKPU_WIFEER(reg_idx)) & ~mask); in wkpu_nxp_s32_disable_interrupt()
153 REG_WRITE(WKPU_WISR(reg_idx), REG_READ(WKPU_WISR(reg_idx)) | mask); in wkpu_nxp_s32_disable_interrupt()
154 REG_WRITE(WKPU_IRER(reg_idx), REG_READ(WKPU_IRER(reg_idx)) & ~mask); in wkpu_nxp_s32_disable_interrupt()
[all …]
Dintc_eirq_nxp_s32.c40 #define REG_WRITE(r, v) sys_write32((v), config->base + (r)) macro
77 REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | mask); in eirq_nxp_s32_interrupt_handler()
135 REG_WRITE(SIUL2_IREER0, reg_val); in eirq_nxp_s32_enable_interrupt()
143 REG_WRITE(SIUL2_IFEER0, reg_val); in eirq_nxp_s32_enable_interrupt()
146 REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | BIT(irq)); in eirq_nxp_s32_enable_interrupt()
147 REG_WRITE(SIUL2_DIRER0, REG_READ(SIUL2_DIRER0) | BIT(irq)); in eirq_nxp_s32_enable_interrupt()
157 REG_WRITE(SIUL2_IREER0, REG_READ(SIUL2_IREER0) & ~BIT(irq)); in eirq_nxp_s32_disable_interrupt()
158 REG_WRITE(SIUL2_IFEER0, REG_READ(SIUL2_IFEER0) & ~BIT(irq)); in eirq_nxp_s32_disable_interrupt()
161 REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | BIT(irq)); in eirq_nxp_s32_disable_interrupt()
162 REG_WRITE(SIUL2_DIRER0, REG_READ(SIUL2_DIRER0) & ~BIT(irq)); in eirq_nxp_s32_disable_interrupt()
[all …]
/Zephyr-latest/drivers/watchdog/
Dwdt_nxp_s32.c82 #define REG_WRITE(r, v) sys_write32((v), config->base + (r)) macro
122 REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_HLK(1U)); in swt_lock()
125 REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_SLK(1U)); in swt_lock()
143 REG_WRITE(SWT_SR, SWT_SR_WSC(SWT_SR_WSC_UNLOCK_KEY1)); in swt_unlock()
144 REG_WRITE(SWT_SR, SWT_SR_WSC(SWT_SR_WSC_UNLOCK_KEY2)); in swt_unlock()
152 REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_SLK(1U)); in swt_unlock()
184 REG_WRITE(SWT_CR, reg_val | in swt_nxp_s32_setup()
190 REG_WRITE(SWT_IR, SWT_IR_TIF(1U)); in swt_nxp_s32_setup()
191 REG_WRITE(SWT_TO, SWT_TO_WTO(data->timeout.period)); in swt_nxp_s32_setup()
192 REG_WRITE(SWT_WN, SWT_WN_WST(data->timeout.window_start)); in swt_nxp_s32_setup()
[all …]
Dxt_wdt_esp32.c110 REG_WRITE(RTC_CNTL_INT_CLR_REG, status); in esp32_xt_wdt_isr()
144 REG_WRITE(RTC_CNTL_INT_ENA_REG, 0); in esp32_xt_wdt_init()
145 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); in esp32_xt_wdt_init()
/Zephyr-latest/soc/nxp/s32/common/
Dmc_rgm.c61 #define REG_WRITE(r, v) sys_write32((v), (mem_addr_t)(DT_INST_REG_ADDR(0) + (r))) macro
71 timeout = !WAIT_FOR(REG_READ(reg) == 0U, MC_RGM_TIMEOUT_US, REG_WRITE(reg, 0xffffffff)); in mc_rgm_clear_reset_status()
95 REG_WRITE(MC_RGM_FERD, 0U); in mc_rgm_init()
100 REG_WRITE(MC_RGM_FRET, MC_RGM_FRET_FRET(DT_INST_PROP(0, func_reset_threshold))); in mc_rgm_init()
102 REG_WRITE(MC_RGM_FRET, MC_RGM_FRET_FRET(0U)); in mc_rgm_init()
108 REG_WRITE(MC_RGM_DRET, MC_RGM_DRET_DRET(DT_INST_PROP(0, dest_reset_threshold))); in mc_rgm_init()
110 REG_WRITE(MC_RGM_DRET, MC_RGM_DRET_DRET(0U)); in mc_rgm_init()
Dmc_me.c80 #define REG_WRITE(r, v) sys_write32((v), (mem_addr_t)(DT_INST_REG_ADDR(0) + (r))) macro
93 REG_WRITE(MC_ME_CTL_KEY, MC_ME_CTL_KEY_KEY(MC_ME_CTL_KEY_DIRECT_KEY)); in mc_me_write_ctl_key()
94 REG_WRITE(MC_ME_CTL_KEY, MC_ME_CTL_KEY_KEY(MC_ME_CTL_KEY_INVERTED_KEY)); in mc_me_write_ctl_key()
99 REG_WRITE(MC_ME_MODE_UPD, MC_ME_MODE_UPD_MODE_UPD(1U)); in mc_me_trigger_mode_update()
109 REG_WRITE(MC_ME_MODE_CONF, MC_ME_MODE_CONF_DEST_RST(1U)); in mc_me_set_mode()
113 REG_WRITE(MC_ME_MODE_CONF, MC_ME_MODE_CONF_FUNC_RST(1U)); in mc_me_set_mode()
/Zephyr-latest/drivers/ethernet/
Deth_dwmac.c198 REG_WRITE(DMA_CHn_TXDESC_TAIL_PTR(0), TXDESC_PHYS_L(d_idx)); in dwmac_send()
390 REG_WRITE(DMA_CHn_RXDESC_TAIL_PTR(0), RXDESC_PHYS_L(d_idx)); in dwmac_rx_refill_thread()
400 REG_WRITE(DMA_CHn_STATUS(ch), status); in dwmac_dma_irq()
464 REG_WRITE(MAC_ADDRESS_HIGH(n), reg_val | MAC_ADDRESS_HIGH_AE); in dwmac_set_mac_addr()
466 REG_WRITE(MAC_ADDRESS_LOW(n), reg_val); in dwmac_set_mac_addr()
492 REG_WRITE(MAC_PKT_FILTER, in dwmac_set_config()
496 REG_WRITE(MAC_PKT_FILTER, in dwmac_set_config()
545 REG_WRITE(DMA_CHn_TX_CTRL(0), reg_val | DMA_CHn_TX_CTRL_St); in dwmac_iface_init()
547 REG_WRITE(DMA_CHn_RX_CTRL(0), reg_val | DMA_CHn_RX_CTRL_SR); in dwmac_iface_init()
550 REG_WRITE(MAC_CONF, reg_val); in dwmac_iface_init()
[all …]
Deth_dwmac_mmu.c69 REG_WRITE(MAC_CONF, in dwmac_platform_init()
73 REG_WRITE(DMA_SYSBUS_MODE, in dwmac_platform_init()
Deth_dwmac_stm32h7x.c104 REG_WRITE(MAC_CONF, in dwmac_platform_init()
108 REG_WRITE(DMA_SYSBUS_MODE, in dwmac_platform_init()
Deth_dwmac_priv.h77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r)) macro
/Zephyr-latest/soc/espressif/esp32c6/
Dhw_init.c50 REG_WRITE(LP_APM_FUNC_CTRL_REG, 0); in hardware_init()
51 REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0); in hardware_init()
52 REG_WRITE(HP_APM_FUNC_CTRL_REG, 0); in hardware_init()
/Zephyr-latest/drivers/counter/
Dcounter_nxp_s32_sys_timer.c48 #define REG_WRITE(r, v) sys_write32((v), config->base + (r)) macro
110 REG_WRITE(STM_CCR(channel), STM_CCR_CEN(0U)); in stm_disable_channel()
111 REG_WRITE(STM_CIR(channel), STM_CIR_CIF(1U)); in stm_disable_channel()
148 REG_WRITE(STM_CMP(channel), ticks); in stm_set_alarm()
149 REG_WRITE(STM_CCR(channel), STM_CCR_CEN(1U)); in stm_set_alarm()
210 REG_WRITE(STM_CNT, 0U); in nxp_s32_sys_timer_start()
211 REG_WRITE(STM_CR, REG_READ(STM_CR) | STM_CR_TEN(1U)); in nxp_s32_sys_timer_start()
220 REG_WRITE(STM_CR, REG_READ(STM_CR) & ~STM_CR_TEN_MASK); in nxp_s32_sys_timer_stop()
354 REG_WRITE(STM_CNT, 0U); in nxp_s32_sys_timer_init()
355 REG_WRITE(STM_CR, in nxp_s32_sys_timer_init()
[all …]
/Zephyr-latest/soc/nxp/s32/s32k3/
Dpmc.c91 #define REG_WRITE(r, v) sys_write32((v), (mem_addr_t)(DT_INST_REG_ADDR(0) + (r))) macro
102 REG_WRITE(PMC_LVSC, 0xffffffffU); in pmc_init()
110 REG_WRITE(PMC_CONFIG, reg_val & ~PMC_CONFIG_LMEN_MASK); in pmc_init()
121 REG_WRITE(PMC_CONFIG, REG_READ(PMC_CONFIG) | PMC_CONFIG_LMEN(1U)); in pmc_init()
123 REG_WRITE(PMC_CONFIG, reg_val); in pmc_init()
/Zephyr-latest/drivers/input/
Dinput_esp32_touch_sensor.c148 REG_WRITE(RTC_CNTL_INT_CLR_REG, status);