40 #define REG_WRITE(r, v) sys_write32((v), config->base + (r))  macro
77 		REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | mask);  in eirq_nxp_s32_interrupt_handler()
135 	REG_WRITE(SIUL2_IREER0, reg_val);  in eirq_nxp_s32_enable_interrupt()
143 	REG_WRITE(SIUL2_IFEER0, reg_val);  in eirq_nxp_s32_enable_interrupt()
146 	REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | BIT(irq));  in eirq_nxp_s32_enable_interrupt()
147 	REG_WRITE(SIUL2_DIRER0, REG_READ(SIUL2_DIRER0) | BIT(irq));  in eirq_nxp_s32_enable_interrupt()
157 	REG_WRITE(SIUL2_IREER0, REG_READ(SIUL2_IREER0) & ~BIT(irq));  in eirq_nxp_s32_disable_interrupt()
158 	REG_WRITE(SIUL2_IFEER0, REG_READ(SIUL2_IFEER0) & ~BIT(irq));  in eirq_nxp_s32_disable_interrupt()
161 	REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | BIT(irq));  in eirq_nxp_s32_disable_interrupt()
162 	REG_WRITE(SIUL2_DIRER0, REG_READ(SIUL2_DIRER0) & ~BIT(irq));  in eirq_nxp_s32_disable_interrupt()
184 	REG_WRITE(SIUL2_IREER0, 0U);  in eirq_nxp_s32_init()
185 	REG_WRITE(SIUL2_IFEER0, 0U);  in eirq_nxp_s32_init()
186 	REG_WRITE(SIUL2_DISR0, 0xffffffff);  in eirq_nxp_s32_init()
187 	REG_WRITE(SIUL2_DIRER0, 0U);  in eirq_nxp_s32_init()
190 	REG_WRITE(SIUL2_DIRSR0, 0U);  in eirq_nxp_s32_init()
193 	REG_WRITE(SIUL2_IFCPR, SIUL2_IFCPR_IFCP(config->filter_clock_prescaler));  in eirq_nxp_s32_init()
197 			REG_WRITE(SIUL2_IFMCR(irq),  in eirq_nxp_s32_init()
199 			REG_WRITE(SIUL2_IFER0, REG_READ(SIUL2_IFER0) | BIT(irq));  in eirq_nxp_s32_init()
201 			REG_WRITE(SIUL2_IFER0, REG_READ(SIUL2_IFER0) & ~BIT(irq));  in eirq_nxp_s32_init()