35 #define REG_WRITE(r, v) sys_write32((v), config->base + (r))  macro
65 		REG_WRITE(WKPU_WISR(irq / 32U), REG_READ(WKPU_WISR(irq / 32U)) | irq_mask);  in wkpu_nxp_s32_interrupt_handler()
125 	REG_WRITE(WKPU_WIREER(reg_idx), reg_val);  in wkpu_nxp_s32_enable_interrupt()
133 	REG_WRITE(WKPU_WIFEER(reg_idx), reg_val);  in wkpu_nxp_s32_enable_interrupt()
136 	REG_WRITE(WKPU_WISR(reg_idx), REG_READ(WKPU_WISR(reg_idx)) | mask);  in wkpu_nxp_s32_enable_interrupt()
137 	REG_WRITE(WKPU_IRER(reg_idx), REG_READ(WKPU_IRER(reg_idx)) | mask);  in wkpu_nxp_s32_enable_interrupt()
149 	REG_WRITE(WKPU_WIREER(reg_idx), REG_READ(WKPU_WIREER(reg_idx)) & ~mask);  in wkpu_nxp_s32_disable_interrupt()
150 	REG_WRITE(WKPU_WIFEER(reg_idx), REG_READ(WKPU_WIFEER(reg_idx)) & ~mask);  in wkpu_nxp_s32_disable_interrupt()
153 	REG_WRITE(WKPU_WISR(reg_idx), REG_READ(WKPU_WISR(reg_idx)) | mask);  in wkpu_nxp_s32_disable_interrupt()
154 	REG_WRITE(WKPU_IRER(reg_idx), REG_READ(WKPU_IRER(reg_idx)) & ~mask);  in wkpu_nxp_s32_disable_interrupt()
175 	REG_WRITE(WKPU_WIREER(0U), 0U);  in wkpu_nxp_s32_init()
176 	REG_WRITE(WKPU_WIFEER(0U), 0U);  in wkpu_nxp_s32_init()
177 	REG_WRITE(WKPU_WISR(0U), 0xffffffff);  in wkpu_nxp_s32_init()
178 	REG_WRITE(WKPU_IRER(0U), 0U);  in wkpu_nxp_s32_init()
181 	REG_WRITE(WKPU_WIFER(0U), (uint32_t)config->filter_enable);  in wkpu_nxp_s32_init()
184 		REG_WRITE(WKPU_WIREER(1U), 0U);  in wkpu_nxp_s32_init()
185 		REG_WRITE(WKPU_WIFEER(1U), 0U);  in wkpu_nxp_s32_init()
186 		REG_WRITE(WKPU_WISR(1U), 0xffffffff);  in wkpu_nxp_s32_init()
187 		REG_WRITE(WKPU_IRER(1U), 0U);  in wkpu_nxp_s32_init()
188 		REG_WRITE(WKPU_WIFER(1U), (uint32_t)(config->filter_enable >> 32U));  in wkpu_nxp_s32_init()