Lines Matching refs:REG_WRITE
198 REG_WRITE(DMA_CHn_TXDESC_TAIL_PTR(0), TXDESC_PHYS_L(d_idx)); in dwmac_send()
390 REG_WRITE(DMA_CHn_RXDESC_TAIL_PTR(0), RXDESC_PHYS_L(d_idx)); in dwmac_rx_refill_thread()
400 REG_WRITE(DMA_CHn_STATUS(ch), status); in dwmac_dma_irq()
464 REG_WRITE(MAC_ADDRESS_HIGH(n), reg_val | MAC_ADDRESS_HIGH_AE); in dwmac_set_mac_addr()
466 REG_WRITE(MAC_ADDRESS_LOW(n), reg_val); in dwmac_set_mac_addr()
492 REG_WRITE(MAC_PKT_FILTER, in dwmac_set_config()
496 REG_WRITE(MAC_PKT_FILTER, in dwmac_set_config()
545 REG_WRITE(DMA_CHn_TX_CTRL(0), reg_val | DMA_CHn_TX_CTRL_St); in dwmac_iface_init()
547 REG_WRITE(DMA_CHn_RX_CTRL(0), reg_val | DMA_CHn_RX_CTRL_SR); in dwmac_iface_init()
550 REG_WRITE(MAC_CONF, reg_val); in dwmac_iface_init()
553 REG_WRITE(DMA_CHn_IRQ_ENABLE(0), in dwmac_iface_init()
582 REG_WRITE(DMA_MODE, DMA_MODE_SWR); in dwmac_probe()
605 REG_WRITE(DMA_CHn_TX_CTRL(0), 0); in dwmac_probe()
606 REG_WRITE(DMA_CHn_RX_CTRL(0), in dwmac_probe()
609 REG_WRITE(DMA_CHn_TXDESC_LIST_HADDR(0), TXDESC_PHYS_H(0)); in dwmac_probe()
610 REG_WRITE(DMA_CHn_TXDESC_LIST_ADDR(0), TXDESC_PHYS_L(0)); in dwmac_probe()
611 REG_WRITE(DMA_CHn_RXDESC_LIST_HADDR(0), RXDESC_PHYS_H(0)); in dwmac_probe()
612 REG_WRITE(DMA_CHn_RXDESC_LIST_ADDR(0), RXDESC_PHYS_L(0)); in dwmac_probe()
613 REG_WRITE(DMA_CHn_TXDESC_RING_LENGTH(0), NB_TX_DESCS - 1); in dwmac_probe()
614 REG_WRITE(DMA_CHn_RXDESC_RING_LENGTH(0), NB_RX_DESCS - 1); in dwmac_probe()