| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32f410_clock.h | 27 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, DCKCFGR2_REG) macro
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| D | stm32l0_clock.h | 75 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) macro
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| D | stm32wb_clock.h | 84 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) macro
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| D | stm32wl_clock.h | 84 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) macro
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| D | stm32u0_clock.h | 82 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) macro
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| D | stm32wba_clock.h | 99 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR3_REG) macro
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| D | stm32g0_clock.h | 83 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) macro
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| D | stm32g4_clock.h | 88 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) macro
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| D | stm32f7_clock.h | 114 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, DCKCFGR2_REG) macro
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| D | stm32l4_clock.h | 89 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) macro
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| D | stm32h7rs_clock.h | 115 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIPR_REG) macro
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| D | stm32h7_clock.h | 126 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, D2CCIP2R_REG) macro
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 75 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
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| D | g0_i2c1_sysclk_lptim1_lsi.overlay | 75 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
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| D | wb_i2c1_hsi_lptim1_lse.overlay | 81 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
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| D | l4_i2c1_hsi_lptim1_lse.overlay | 83 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
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| D | l4_i2c1_sysclk_lptim1_lsi.overlay | 83 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
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| D | wl_i2c1_sysclk_lptim1_lsi.overlay | 80 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
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| D | wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 94 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
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| /Zephyr-latest/boards/makerbase/mks_canable_v20/ |
| D | mks_canable_v20.dts | 69 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
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| /Zephyr-latest/boards/st/nucleo_g431kb/ |
| D | nucleo_g431kb.dts | 57 <&rcc STM32_SRC_LSI LPTIM1_SEL(3)>;
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| /Zephyr-latest/boards/seeed/lora_e5_mini/ |
| D | lora_e5_mini.dts | 51 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
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| /Zephyr-latest/drivers/timer/ |
| D | stm32_lptim_timer.c | 40 {.bus = STM32_SRC_LSI, .enr = LPTIM1_SEL(1)}
42 {.bus = STM32_SRC_LSE, .enr = LPTIM1_SEL(3)}
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| /Zephyr-latest/boards/olimex/lora_stm32wl_devkit/ |
| D | olimex_lora_stm32wl_devkit.dts | 50 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
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| /Zephyr-latest/boards/st/nucleo_wba52cg/ |
| D | nucleo_wba52cg.dts | 135 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
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