1/*
2 * Copyright (c) 2022 Martin Jäger <martin@libre.solar>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <olimex/bb-stm32wl.dtsi>
9#include <zephyr/dt-bindings/input/input-event-codes.h>
10
11/ {
12	model = "Olimex LoRa STM32WL DevKit";
13	compatible = "olimex,lora-stm32wl-devkit";
14
15	chosen {
16		zephyr,console = &usart1;
17		zephyr,shell-uart = &usart1;
18		zephyr,sram = &sram0;
19		zephyr,flash = &flash0;
20		zephyr,code-partition = &slot0_partition;
21	};
22
23	leds {
24		compatible = "gpio-leds";
25		green_led_1: led_0 {
26			gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>;
27			label = "User LED1";
28		};
29	};
30
31	gpio_keys {
32		compatible = "gpio-keys";
33		user_button: button_0 {
34			label = "SW2";
35			gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
36			zephyr,code = <INPUT_KEY_0>;
37		};
38	};
39
40	aliases {
41		led0 = &green_led_1;
42		sw0 = &user_button;
43		lora0 = &lora;
44		watchdog0 = &iwdg;
45	};
46};
47
48stm32_lp_tick_source: &lptim1 {
49	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
50		 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
51	status = "okay";
52};
53
54&clk_lsi {
55	status = "okay";
56};
57
58&pll {
59	div-m = <1>;
60	mul-n = <6>;
61	div-r = <2>;
62	div-q = <2>;
63	clocks = <&clk_hsi>;
64	status = "okay";
65};
66
67&rcc {
68	clocks = <&pll>;
69	clock-frequency = <DT_FREQ_M(48)>;
70	cpu1-prescaler = <1>;
71	ahb3-prescaler = <1>;
72	apb1-prescaler = <1>;
73	apb2-prescaler = <1>;
74};
75
76uext_serial: &lpuart1 {
77	pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
78	pinctrl-names = "default";
79	current-speed = <115200>;
80	status = "okay";
81};
82
83&usart1 {
84	pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
85	pinctrl-names = "default";
86	current-speed = <115200>;
87	status = "okay";
88};
89
90uext_i2c: &i2c1 {
91	pinctrl-0 = <&i2c1_scl_pa9 &i2c1_sda_pa10>;
92	pinctrl-names = "default";
93	status = "okay";
94	clock-frequency = <I2C_BITRATE_FAST>;
95
96	bme280: bme280@77 {
97		compatible = "bosch,bme280";
98		status = "okay";
99		reg = <0x77>;
100	};
101
102	iis2mdc@1e {
103		compatible = "st,iis2mdc";
104		reg = <0x1e>;
105		drdy-gpios =  <&gpioa 8 GPIO_ACTIVE_HIGH>;
106	};
107};
108
109uext_spi: &spi1 {
110	pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
111		     &spi1_miso_pa11 &spi1_mosi_pa7>;
112	pinctrl-names = "default";
113	status = "okay";
114};
115
116&rtc {
117	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
118		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
119	status = "okay";
120};
121
122&iwdg {
123	status = "okay";
124};
125
126&aes {
127	status = "okay";
128};
129
130&rng {
131	status = "okay";
132};
133
134&flash0 {
135	partitions {
136		compatible = "fixed-partitions";
137		#address-cells = <1>;
138		#size-cells = <1>;
139
140		boot_partition: partition@0 {
141			label = "mcuboot";
142			reg = <0x00000000 DT_SIZE_K(32)>;
143			read-only;
144		};
145		slot0_partition: partition@8000 {
146			label = "image-0";
147			reg = <0x00008000 DT_SIZE_K(108)>;
148		};
149		slot1_partition: partition@23000 {
150			label = "image-1";
151			reg = <0x00023000 DT_SIZE_K(108)>;
152		};
153		storage_partition: partition@3e000 {
154			label = "storage";
155			reg = <0x0003e000 DT_SIZE_K(8)>;
156		};
157	};
158};
159