Home
last modified time | relevance | path

Searched refs:L2_SRAM_SIZE (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/drivers/mm/
Dmm_drv_intel_adsp.h54 #define L2_SRAM_PAGES_NUM (L2_SRAM_SIZE / CONFIG_MM_DRV_PAGE_SIZE)
57 #define L2_SRAM_BANK_NUM (L2_SRAM_SIZE / SRAM_BANK_SIZE)
Dmm_drv_intel_adsp_mtl_tlb.c222 (pa >= (L2_SRAM_BASE + L2_SRAM_SIZE))) { in sys_mm_drv_map_page()
392 if ((pa >= L2_SRAM_BASE) && (pa < (L2_SRAM_BASE + L2_SRAM_SIZE))) { in sys_mm_drv_unmap_page_wflush()
777 if (L2_SRAM_BASE + L2_SRAM_SIZE < UNUSED_L2_START_ALIGNED || in sys_mm_drv_mm_init()
940 return L2_SRAM_SIZE + TLB_SIZE + (L2_SRAM_PAGES_NUM * sizeof(void *)) in adsp_mm_get_storage_size()
Dmm_drv_intel_adsp_tlb.c96 (pa >= (L2_SRAM_BASE + L2_SRAM_SIZE))) { in sys_mm_drv_map_page()
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Dadsp_memory.h13 #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) macro
22 #define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dboot.c48 hp_sram_init(L2_SRAM_SIZE); in boot_d3_restore()
Dsram.c32 bbzero((void *)L2_SRAM_BASE, L2_SRAM_SIZE); in hp_sram_init()
Dace-link.ld545 . = L2_SRAM_BASE + L2_SRAM_SIZE;
/Zephyr-latest/soc/intel/intel_adsp/common/
Dboot.c96 mod->segment[i].v_base_addr >= L2_SRAM_BASE + L2_SRAM_SIZE || in parse_module()
167 hp_sram_init(L2_SRAM_SIZE); in boot_core0()
/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Dadsp_memory.h16 #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) macro
28 #define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dsram.c110 bbzero((void *)L2_SRAM_BASE, L2_SRAM_SIZE); in hp_sram_init()
/Zephyr-latest/tests/boards/intel_adsp/mm/src/
Dmain.c40 void *va = (void *)ROUND_UP(L2_SRAM_BASE + L2_SRAM_SIZE, PAGE_SZ);
166 void *va = (void *)ROUND_UP(L2_SRAM_BASE + L2_SRAM_SIZE, PAGE_SZ); in ZTEST()
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/
Dxtensa-cavs-linker.ld432 . = L2_SRAM_BASE + L2_SRAM_SIZE;