1 /* Copyright(c) 2021 Intel Corporation. All rights reserved.
2  * SPDX-License-Identifier: Apache-2.0
3  */
4 
5 #include <stddef.h>
6 #include <stdint.h>
7 
8 #include <zephyr/devicetree.h>
9 #include <soc_util.h>
10 #include <zephyr/cache.h>
11 #include <adsp_shim.h>
12 #include <adsp_memory.h>
13 #include <cpu_init.h>
14 #include "manifest.h"
15 
hp_sram_init(uint32_t memory_size)16 __imr void hp_sram_init(uint32_t memory_size)
17 {
18 	ARG_UNUSED(memory_size);
19 
20 	uint32_t hpsram_ebb_quantity = ace_hpsram_get_bank_count();
21 	uint32_t idx;
22 
23 	for (idx = 0; idx < hpsram_ebb_quantity; ++idx) {
24 		HPSRAM_REGS(idx)->HSxPGCTL = 0;
25 		HPSRAM_REGS(idx)->HSxRMCTL = IS_ENABLED(CONFIG_SRAM_RETENTION_MODE);
26 	}
27 	for (idx = 0; idx < hpsram_ebb_quantity; ++idx) {
28 		while (HPSRAM_REGS(idx)->HSxPGISTS != 0) {
29 		}
30 	}
31 
32 	bbzero((void *)L2_SRAM_BASE, L2_SRAM_SIZE);
33 }
34 
lp_sram_init(void)35 __imr void lp_sram_init(void)
36 {
37 	uint32_t lpsram_ebb_quantity = ace_lpsram_get_bank_count();
38 	uint32_t idx;
39 
40 	for (idx = 0; idx < lpsram_ebb_quantity; ++idx) {
41 		LPSRAM_REGS(idx)->USxPGCTL = 0;
42 		LPSRAM_REGS(idx)->USxRMCTL = IS_ENABLED(CONFIG_SRAM_RETENTION_MODE);
43 	}
44 	for (idx = 0; idx < lpsram_ebb_quantity; ++idx) {
45 		while (LPSRAM_REGS(idx)->USxPGISTS != 0) {
46 		}
47 	}
48 
49 	bbzero((void *)LP_SRAM_BASE, LP_SRAM_SIZE);
50 }
51