1 /* 2 * Copyright (c) 2022 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief Header for agregating all defines for mm 10 * 11 */ 12 #ifndef ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_ 13 #define ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_ 14 15 #define DT_DRV_COMPAT intel_adsp_mtl_tlb 16 17 #include <zephyr/device.h> 18 #include <zephyr/kernel.h> 19 #include <zephyr/spinlock.h> 20 #include <zephyr/sys/__assert.h> 21 #include <zephyr/sys/check.h> 22 #include <zephyr/kernel/mm.h> 23 #include <zephyr/sys/util.h> 24 #include <zephyr/drivers/mm/system_mm.h> 25 #include <zephyr/sys/mem_blocks.h> 26 27 #include <soc.h> 28 #include <adsp_memory.h> 29 #include <adsp_memory_regions.h> 30 31 #include "mm_drv_common.h" 32 33 #define TLB_BASE (mm_reg_t)DT_REG_ADDR(DT_NODELABEL(tlb)) 34 35 /* 36 * Number of significant bits in the page index (defines the size of 37 * the table) 38 */ 39 #define TLB_PADDR_SIZE DT_INST_PROP(0, paddr_size) 40 #define TLB_EXEC_BIT BIT(DT_INST_PROP(0, exec_bit_idx)) 41 #define TLB_WRITE_BIT BIT(DT_INST_PROP(0, write_bit_idx)) 42 43 #define TLB_ENTRY_NUM (1 << TLB_PADDR_SIZE) 44 #define TLB_PADDR_MASK ((1 << TLB_PADDR_SIZE) - 1) 45 #define TLB_ENABLE_BIT BIT(TLB_PADDR_SIZE) 46 47 /* This is used to translate from TLB entry back to physical address. */ 48 /* base address of TLB table */ 49 #define TLB_PHYS_BASE \ 50 (((L2_SRAM_BASE / CONFIG_MM_DRV_PAGE_SIZE) & ~TLB_PADDR_MASK) * CONFIG_MM_DRV_PAGE_SIZE) 51 #define HPSRAM_SEGMENTS(hpsram_ebb_quantity) \ 52 ((ROUND_DOWN((hpsram_ebb_quantity) + 31u, 32u) / 32u) - 1u) 53 54 #define L2_SRAM_PAGES_NUM (L2_SRAM_SIZE / CONFIG_MM_DRV_PAGE_SIZE) 55 #define MAX_EBB_BANKS_IN_SEGMENT 32 56 #define SRAM_BANK_SIZE (128 * 1024) 57 #define L2_SRAM_BANK_NUM (L2_SRAM_SIZE / SRAM_BANK_SIZE) 58 #define IS_BIT_SET(value, idx) ((value) & (1 << (idx))) 59 60 /** 61 * Calculate TLB entry based on physical address. 62 * 63 * @param pa Page-aligned virutal address. 64 * @return TLB entry value. 65 */ pa_to_tlb_entry(uintptr_t pa)66static inline uint16_t pa_to_tlb_entry(uintptr_t pa) 67 { 68 return (((pa) / CONFIG_MM_DRV_PAGE_SIZE) & TLB_PADDR_MASK); 69 } 70 71 /** 72 * Calculate physical address based on TLB entry. 73 * 74 * @param tlb_entry TLB entry value. 75 * @return physcial address pointer. 76 */ tlb_entry_to_pa(uint16_t tlb_entry)77static inline uintptr_t tlb_entry_to_pa(uint16_t tlb_entry) 78 { 79 return ((((tlb_entry) & TLB_PADDR_MASK) * 80 CONFIG_MM_DRV_PAGE_SIZE) + TLB_PHYS_BASE); 81 } 82 83 /** 84 * Calculate virtual memory regions allocation based on 85 * info from linker script. 86 * 87 * @param End address of staticaly allocated memory. 88 * @return Error Code. 89 */ 90 int calculate_memory_regions(uintptr_t static_alloc_end_ptr); 91 92 #endif /* ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_ */ 93
