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Searched refs:L2_SRAM_BASE (Results 1 – 14 of 14) sorted by relevance

/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dmem_window.h23 #define HP_SRAM_WIN0_BASE L2_SRAM_BASE + WIN0_OFFSET
26 #define HP_SRAM_WIN1_BASE L2_SRAM_BASE + WIN1_OFFSET
29 #define HP_SRAM_WIN2_BASE L2_SRAM_BASE + WIN2_OFFSET
32 #define HP_SRAM_WIN3_BASE L2_SRAM_BASE + WIN3_OFFSET
Dadsp-vectors.h11 (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE)
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Dadsp_memory.h12 #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) macro
21 #define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
/Zephyr-latest/drivers/mm/
Dmm_drv_intel_adsp_mtl_tlb.c63 (uint8_t *) L2_SRAM_BASE);
85 uint32_t phys_offset = pa - L2_SRAM_BASE; in get_hpsram_bank_idx()
221 CHECKIF((pa < L2_SRAM_BASE) || in sys_mm_drv_map_page()
222 (pa >= (L2_SRAM_BASE + L2_SRAM_SIZE))) { in sys_mm_drv_map_page()
392 if ((pa >= L2_SRAM_BASE) && (pa < (L2_SRAM_BASE + L2_SRAM_SIZE))) { in sys_mm_drv_unmap_page_wflush()
753 (void *) L2_SRAM_BASE, L2_SRAM_PAGES_NUM); in sys_mm_drv_mm_init()
777 if (L2_SRAM_BASE + L2_SRAM_SIZE < UNUSED_L2_START_ALIGNED || in sys_mm_drv_mm_init()
778 L2_SRAM_BASE > UNUSED_L2_START_ALIGNED) { in sys_mm_drv_mm_init()
828 phys_addr = POINTER_TO_UINT(L2_SRAM_BASE) + in adsp_mm_save_context()
905 uint32_t phys_offset = phys_addr - L2_SRAM_BASE; in adsp_mm_restore_context()
Dmm_drv_intel_adsp_tlb.c95 CHECKIF((pa < L2_SRAM_BASE) || in sys_mm_drv_map_page()
96 (pa >= (L2_SRAM_BASE + L2_SRAM_SIZE))) { in sys_mm_drv_map_page()
236 *phys = (ent & TLB_PADDR_MASK) * CONFIG_MM_DRV_PAGE_SIZE + L2_SRAM_BASE; in sys_mm_drv_page_phys_get()
Dmm_drv_intel_adsp.h50 (((L2_SRAM_BASE / CONFIG_MM_DRV_PAGE_SIZE) & ~TLB_PADDR_MASK) * CONFIG_MM_DRV_PAGE_SIZE)
/Zephyr-latest/soc/intel/intel_adsp/common/
Dboot.c96 mod->segment[i].v_base_addr >= L2_SRAM_BASE + L2_SRAM_SIZE || in parse_module()
97 mod->segment[i].v_base_addr < L2_SRAM_BASE) { in parse_module()
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dsram.c32 bbzero((void *)L2_SRAM_BASE, L2_SRAM_SIZE); in hp_sram_init()
Dmmu_ace30.c36 .start = (uint32_t)L2_SRAM_BASE,
Dace-link.ld548 . = L2_SRAM_BASE + L2_SRAM_SIZE;
/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Dadsp_memory.h15 #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) macro
27 #define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dsram.c110 bbzero((void *)L2_SRAM_BASE, L2_SRAM_SIZE); in hp_sram_init()
/Zephyr-latest/tests/boards/intel_adsp/mm/src/
Dmain.c40 void *va = (void *)ROUND_UP(L2_SRAM_BASE + L2_SRAM_SIZE, PAGE_SZ);
166 void *va = (void *)ROUND_UP(L2_SRAM_BASE + L2_SRAM_SIZE, PAGE_SZ); in ZTEST()
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/
Dxtensa-cavs-linker.ld432 . = L2_SRAM_BASE + L2_SRAM_SIZE;