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Searched refs:GD32_RESET_TIMER7 (Results 1 – 11 of 11) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dgd32vf103.h39 #define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U) macro
Dgd32a50x.h65 #define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U) macro
Dgd32e10x.h40 #define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U) macro
Dgd32f403.h42 #define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U) macro
Dgd32e50x.h42 #define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U) macro
Dgd32f4xx.h92 #define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 1U) macro
/Zephyr-latest/dts/arm/gd/gd32e50x/
Dgd32e507xe.dtsi18 resets = <&rctl GD32_RESET_TIMER7>;
/Zephyr-latest/dts/arm/gd/gd32a50x/
Dgd32a50x.dtsi347 resets = <&rctl GD32_RESET_TIMER7>;
/Zephyr-latest/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi354 resets = <&rctl GD32_RESET_TIMER7>;
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi378 resets = <&rctl GD32_RESET_TIMER7>;
/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi506 resets = <&rctl GD32_RESET_TIMER7>;