Home
last modified time | relevance | path

Searched refs:GD32_RESET_TIMER3 (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dgd32vf103.h45 #define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U) macro
Dgd32e10x.h49 #define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U) macro
Dgd32f403.h51 #define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U) macro
Dgd32e50x.h55 #define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U) macro
Dgd32f4xx.h65 #define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U) macro
/Zephyr-latest/dts/riscv/gd/
Dgd32vf103.dtsi357 resets = <&rctl GD32_RESET_TIMER3>;
/Zephyr-latest/dts/arm/gd/gd32e50x/
Dgd32e50x.dtsi355 resets = <&rctl GD32_RESET_TIMER3>;
/Zephyr-latest/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi298 resets = <&rctl GD32_RESET_TIMER3>;
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi339 resets = <&rctl GD32_RESET_TIMER3>;
/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi449 resets = <&rctl GD32_RESET_TIMER3>;