Searched refs:GD32_RESET_TIMER2 (Results 1 – 12 of 12) sorted by relevance
41 #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) macro
42 #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) macro
44 #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) macro
48 #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) macro
50 #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) macro
54 #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) macro
64 #define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U) macro
340 resets = <&rctl GD32_RESET_TIMER2>;
338 resets = <&rctl GD32_RESET_TIMER2>;
281 resets = <&rctl GD32_RESET_TIMER2>;
322 resets = <&rctl GD32_RESET_TIMER2>;
432 resets = <&rctl GD32_RESET_TIMER2>;
