Searched refs:GD32_RESET_TIMER1 (Results 1 – 12 of 12) sorted by relevance
40 #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) macro
41 #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) macro
43 #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) macro
45 #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) macro
47 #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) macro
53 #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) macro
63 #define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U) macro
307 resets = <&rctl GD32_RESET_TIMER1>;
323 resets = <&rctl GD32_RESET_TIMER1>;
320 resets = <&rctl GD32_RESET_TIMER1>;
264 resets = <&rctl GD32_RESET_TIMER1>;
414 resets = <&rctl GD32_RESET_TIMER1>;
