Searched refs:CPU0 (Results 1 – 20 of 20) sorted by relevance
8 # for CPU0, which will boot the device and wake up CPU1.10 # any binary for CPU0, as this is built by the dual core sample.
38 (CPU0 and CPU1). Zephyr provides support for building firmware39 images for both CPU0 and CPU1. For CPU0 supporting ARM Security Extensions47 | mps2/an521/cpu0 | For building Secure (or Secure-only) firmware on CPU0 |49 | mps2/an521/cpu0/ns | For building Non-Secure firmware for CPU0 |387 MPS2+ AN521 (CPU0) supports the Armv8m Security Extension.396 Applications on the MPS2+ AN521 (CPU0) may contain a Secure and a Non-Secure403 By default the Secure image for the MPS2+ AN521 (CPU0) is built413 for MPS2+ AN521 (CPU0) using ``-DBOARD=mps2/an521/cpu0/ns``.436 1. Build the Secure Zephyr application for MPS2+ AN521 (CPU0)440 2. Build the Non-Secure Zephyr application for MPS2+ AN521 (CPU0)[all …]
97 | DMA | on-chip | dma (on CPU0) |106 CPU0 is the only target that can run standalone.108 - *lpcxpresso55s69/lpc55s69/cpu0* secure (S) address space for CPU0109 - *lpcxpresso55s69/lpc55s69/cpu0/ns* non-secure (NS) address space for CPU0112 NS target for CPU0 does not work correctly without a secure image to configure118 CPU1 does not work without CPU0 enabling it.237 | CPU0 | 0x00000000[630K] | CPU0, can access all flash |245 | sram0 | 0x20000000[64k] | CPU0 memory |
216 uint32_t volatile CPU0; in hal_radio_ram_prio_setup() member228 NRF_AMLI->RAMPRI.CPU0 = 0xFFFFFFFFUL; in hal_radio_ram_prio_setup()
225 uint32_t volatile CPU0; in hal_radio_ram_prio_setup() member242 NRF_AMLI->RAMPRI.CPU0 = 0xFFFFFFFFUL; in hal_radio_ram_prio_setup()
223 uint32_t volatile CPU0; in hal_radio_ram_prio_setup() member240 NRF_AMLI->RAMPRI.CPU0 = 0xFFFFFFFFUL; in hal_radio_ram_prio_setup()
386 uint32_t volatile CPU0; in hal_radio_ram_prio_setup() member398 NRF_AMLI->RAMPRI.CPU0 = 0xFFFFFFFFUL; in hal_radio_ram_prio_setup()
386 uint32_t volatile CPU0; in hal_radio_ram_prio_setup() member403 NRF_AMLI->RAMPRI.CPU0 = 0xFFFFFFFFUL; in hal_radio_ram_prio_setup()
385 uint32_t volatile CPU0; in hal_radio_ram_prio_setup() member402 NRF_AMLI->RAMPRI.CPU0 = 0xFFFFFFFFUL; in hal_radio_ram_prio_setup()
376 uint32_t volatile CPU0; in hal_radio_ram_prio_setup() member393 NRF_AMLI->RAMPRI.CPU0 = 0xFFFFFFFFUL; in hal_radio_ram_prio_setup()
43 ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU0
114 | CPU0 | 0x10000000[1856K] | primary core flash |122 | srama | 0x20000000[320k] | CPU0 ram |134 only enables the first core. CPU0 is the only target that can run standalone.136 CPU1 does not work without CPU0 enabling it.
152 This configures ACRN to run Zephyr on CPU0 and CPU1. The ACRN hypervisor156 Since Zephyr is using CPU0 and CPU1, we also have to change
246 CPU0 and T1 not be pinned. If CPU0 is executing T2 and CPU1 executing T1,247 then this set is is both valid and optimal. However, if CPU0 is executing
142 - CPU0 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0)
153 - CPU0 (Cortex-M7) boot address is set to 0x08000000 (OB: BOOT_CM7_ADD0)
170 - CPU0 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0)
229 for the primary processor (CPU0) is 40MHz.
223 for the primary processor (CPU0) is 50MHz.
82 * The SRAM region [0x180000-0x1FFFFF] is reserved for CPU0 application, last
