1.. zephyr:board:: lpcxpresso55s69 2 3Overview 4******** 5 6The LPCXpresso55S69 development board provides the ideal platform for evaluation 7of and development with the LPC55S6x MCU based on the Arm® Cortex®-M33 8architecture. The board includes a high performance onboard debug probe, audio 9subsystem, and accelerometer, with several options for adding off-the-shelf 10add-on boards for networking, sensors, displays, and other interfaces. 11 12Hardware 13******** 14 15- LPC55S69 dual core Arm Cortex-M33 microcontroller running at up to 100 MHz 16- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP and SEGGER J-Link 17 protocol options 18- UART and SPI port bridging from LPC55S69 target to USB via the onboard debug 19 probe 20- Hardware support for external debug probe 21- 3 x user LEDs, plus Reset, ISP (3) and user buttons 22- Micro SD card slot (4-bit SDIO) 23- NXP MMA8652FCR1 accelerometer 24- Stereo audio codec with line in/out 25- High and full speed USB ports with micro A/B connector for host or device 26 functionality 27- MikroEletronika Click expansion option 28- LPCXpresso-V3 expansion option compatible with Arduino UNO 29- PMod compatible expansion / host connector 30 31For more information about the LPC55S69 SoC and LPCXPRESSO55S69 board, see: 32 33- `LPC55S69 SoC Website`_ 34- `LPC55S69 Datasheet`_ 35- `LPC55S69 Reference Manual`_ 36- `LPCXPRESSO55S69 Website`_ 37- `LPCXPRESSO55S69 User Guide`_ 38- `LPCXPRESSO55S69 Schematics`_ 39- `LPCXPRESSO55S69 Debug Firmware`_ 40 41Supported Features 42================== 43 44NXP considers the LPCXpresso55S69 as the superset board for the LPC55xx 45series of MCUs. This board is a focus for NXP's Full Platform Support for 46Zephyr, to better enable the entire LPC55xx series. NXP prioritizes enabling 47this board with new support for Zephyr features. The lpcxpresso55s69 board 48configuration supports the following hardware features: 49 50+-----------+------------+-------------------------------------+ 51| Interface | Controller | Driver/Component | 52+===========+============+=====================================+ 53| NVIC | on-chip | nested vector interrupt controller | 54+-----------+------------+-------------------------------------+ 55| SYSTICK | on-chip | systick | 56+-----------+------------+-------------------------------------+ 57| IOCON | on-chip | pinmux | 58+-----------+------------+-------------------------------------+ 59| GPIO | on-chip | gpio | 60+-----------+------------+-------------------------------------+ 61| I2C | on-chip | i2c | 62+-----------+------------+-------------------------------------+ 63| SPI | on-chip | spi | 64+-----------+------------+-------------------------------------+ 65| USART | on-chip | serial port-polling; | 66| | | serial port-interrupt | 67+-----------+------------+-------------------------------------+ 68| WWDT | on-chip | windowed watchdog timer | 69+-----------+------------+-------------------------------------+ 70| TrustZone | on-chip | Trusted Firmware-M | 71+-----------+------------+-------------------------------------+ 72| ADC | on-chip | adc | 73+-----------+------------+-------------------------------------+ 74| CLOCK | on-chip | clock_control | 75+-----------+------------+-------------------------------------+ 76| MAILBOX | on-chip | ipm | 77+-----------+------------+-------------------------------------+ 78| HWINFO | on-chip | Unique device serial number | 79+-----------+------------+-------------------------------------+ 80| USB HS | on-chip | USB High Speed device | 81+-----------+------------+-------------------------------------+ 82| USB FS | on-chip | USB Full Speed device | 83+-----------+------------+-------------------------------------+ 84| COUNTER | on-chip | counter | 85+-----------+------------+-------------------------------------+ 86| I2S | on-chip | i2s | 87+-----------+------------+-------------------------------------+ 88| PWM | on-chip | pwm | 89+-----------+------------+-------------------------------------+ 90| RNG | on-chip | entropy; | 91| | | random | 92+-----------+------------+-------------------------------------+ 93| IAP | on-chip | flash programming | 94+-----------+------------+-------------------------------------+ 95| SDIF | on-chip | sdhc | 96+-----------+------------+-------------------------------------+ 97| DMA | on-chip | dma (on CPU0) | 98+-----------+------------+-------------------------------------+ 99 100Targets available 101================== 102 103The default configuration file 104:zephyr_file:`boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig` 105only enables the first core. 106CPU0 is the only target that can run standalone. 107 108- *lpcxpresso55s69/lpc55s69/cpu0* secure (S) address space for CPU0 109- *lpcxpresso55s69/lpc55s69/cpu0/ns* non-secure (NS) address space for CPU0 110- *lpcxpresso55s69/lpc55s69/cpu1* CPU1 target, no security extensions 111 112NS target for CPU0 does not work correctly without a secure image to configure 113the system, then hand execution over to the NS environment. To enable a secure 114image, run any of the ``tfm_integration`` samples. When using the NS target 115``CONFIG_BUILD_WITH_TFM`` is always enabled to ensure that a valid S image is 116included during the build process. 117 118CPU1 does not work without CPU0 enabling it. 119To enable it, run one of the following samples in ``subsys\ipc``: 120 121- ``ipm_mcux`` 122- ``openamp`` 123 124Connections and IOs 125=================== 126 127The LPC55S69 SoC has IOCON registers, which can be used to configure the 128functionality of a pin. 129 130+---------+-----------------+----------------------------+ 131| Name | Function | Usage | 132+=========+=================+============================+ 133| PIO0_26 | SPI | SPI MOSI | 134+---------+-----------------+----------------------------+ 135| PIO0_27 | USART | USART TX | 136+---------+-----------------+----------------------------+ 137| PIO0_29 | USART | USART RX | 138+---------+-----------------+----------------------------+ 139| PIO0_30 | USART | USART TX | 140+---------+-----------------+----------------------------+ 141| PIO1_1 | SPI | SPI SSEL | 142+---------+-----------------+----------------------------+ 143| PIO1_2 | SPI | SPI SCK | 144+---------+-----------------+----------------------------+ 145| PIO1_3 | SPI | SPI MISO | 146+---------+-----------------+----------------------------+ 147| PIO1_4 | GPIO | RED LED | 148+---------+-----------------+----------------------------+ 149| PIO1_6 | GPIO | BLUE_LED | 150+---------+-----------------+----------------------------+ 151| PIO1_7 | GPIO | GREEN LED | 152+---------+-----------------+----------------------------+ 153| PIO1_20 | I2C | I2C SCL | 154+---------+-----------------+----------------------------+ 155| PIO1_21 | I2C | I2C SDA | 156+---------+-----------------+----------------------------+ 157| PIO1_24 | USART | USART RX | 158+---------+-----------------+----------------------------+ 159| PIO0_20 | I2S | I2S DATAOUT | 160+---------+-----------------+----------------------------+ 161| PIO0_19 | I2S | I2S TX WS | 162+---------+-----------------+----------------------------+ 163| PIO0_21 | I2S | I2S TX SCK | 164+---------+-----------------+----------------------------+ 165| PIO1_13 | I2S | I2S DATAIN | 166+---------+-----------------+----------------------------+ 167| PIO0_15 | SCT0_OUT2 | PWM | 168+---------+-----------------+----------------------------+ 169| PIO0_24 | SD0_D0 | SDHC | 170+---------+-----------------+----------------------------+ 171| PIO0_25 | SD0_D1 | SDHC | 172+---------+-----------------+----------------------------+ 173| PIO0_31 | SD0_D2 | SDHC | 174+---------+-----------------+----------------------------+ 175| PIO0_7 | SD0_CLK | SDHC | 176+---------+-----------------+----------------------------+ 177| PIO0_8 | SD0_CMD | SDHC | 178+---------+-----------------+----------------------------+ 179| PIO0_9 | SD0_POW_EN | SDHC | 180+---------+-----------------+----------------------------+ 181| PIO1_0 | SD0_D3 | SDHC | 182+---------+-----------------+----------------------------+ 183 184Memory mappings 185=============== 186 187There are multiple memory configurations, they all start from the 188MCUboot partitioning which looks like the table below 189 190+----------+------------------+---------------------------------+ 191| Name | Address[Size] | Comment | 192+==========+==================+=================================+ 193| boot | 0x00000000[32K] | Bootloader | 194+----------+------------------+---------------------------------+ 195| slot0 | 0x00008000[160k] | Image that runs after boot | 196+----------+------------------+---------------------------------+ 197| slot0_ns | 0x00030000[96k] | Second image, core 1 or NS | 198+----------+------------------+---------------------------------+ 199| slot1 | 0x00048000[160k] | Updates slot0 image | 200+----------+------------------+---------------------------------+ 201| slot1_ns | 0x00070000[96k] | Updates slot0_ns image | 202+----------+------------------+---------------------------------+ 203| storage | 0x00088000[50k] | File system, persistent storage | 204+----------+------------------+---------------------------------+ 205 206See below examples of how this partitioning is used 207 208Trusted Execution 209***************** 210 211+-----------+------------------+--------------------+ 212| Memory | Address[Size] | Comment | 213+===========+==================+====================+ 214| MCUboot | 0x00000000[32K] | Secure bootloader | 215+-----------+------------------+--------------------+ 216| TFM_S | 0x00008000[160k] | Secure image | 217+-----------+------------------+--------------------+ 218| Zephyr_NS | 0x00030000[96k] | Non-Secure image | 219+-----------+------------------+--------------------+ 220| storage | 0x00088000[50k] | Persistent storage | 221+-----------+------------------+--------------------+ 222 223+----------------+------------------+-------------------+ 224| RAM | Address[Size] | Comment | 225+================+==================+===================+ 226| secure_ram | 0x20000000[136k] | Secure memory | 227+----------------+------------------+-------------------+ 228| non_secure_ram | 0x20022000[136k] | Non-Secure memory | 229+----------------+------------------+-------------------+ 230 231Dual Core samples 232***************** 233 234+--------+------------------+----------------------------+ 235| Memory | Address[Size] | Comment | 236+========+==================+============================+ 237| CPU0 | 0x00000000[630K] | CPU0, can access all flash | 238+--------+------------------+----------------------------+ 239| CPU1 | 0x00030000[96k] | CPU1, has no MPU | 240+--------+------------------+----------------------------+ 241 242+-------+------------------+-----------------------+ 243| RAM | Address[Size] | Comment | 244+=======+==================+=======================+ 245| sram0 | 0x20000000[64k] | CPU0 memory | 246+-------+------------------+-----------------------+ 247| sram3 | 0x20030000[64k] | CPU1 memory | 248+-------+------------------+-----------------------+ 249| sram4 | 0x20040000[16k] | Mailbox/shared memory | 250+-------+------------------+-----------------------+ 251 252System Clock 253============ 254 255The LPC55S69 SoC is configured to use PLL1 clocked from the external 16MHz 256crystal, running at 144MHz as a source for the system clock. When the flash 257controller is enabled, the core clock will be reduced to 96MHz. The application 258may reconfigure clocks after initialization, provided that the core clock is 259always set to 96MHz when flash programming operations are performed. 260 261Serial Port 262=========== 263 264The LPC55S69 SoC has 8 FLEXCOMM interfaces for serial communication. One is 265configured as USART for the console and the remaining are not used. 266 267Programming and Debugging 268************************* 269 270Build and flash applications as usual (see :ref:`build_an_application` and 271:ref:`application_run` for more details). 272 273Configuring a Debug Probe 274========================= 275 276LinkServer is the default runner for this board. 277A debug probe is used for both flashing and debugging the board. This board is 278configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe, 279however the :ref:`pyocd-debug-host-tools` does not yet support this probe so you 280must reconfigure the board for one of the following debug probes instead. 281 282:ref:`lpclink2-jlink-onboard-debug-probe` 283----------------------------------------- 284 285Install the :ref:`jlink-debug-host-tools` and make sure they are in your search 286path. 287 288Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program 289the J-Link firmware. Please make sure you have the latest firmware for this 290board. 291 292:ref:`lpclink2-cmsis-onboard-debug-probe` 293----------------------------------------- 294 295 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. 296 2. To update the debug firmware, please follow the instructions on `LPCXPRESSO55S69 Debug Firmware`_ 297 298:ref:`opensda-daplink-onboard-debug-probe` 299------------------------------------------ 300 301PyOCD support for this board is ongoing and not yet available. 302To use DAPLink's flash memory programming on this board, follow the instructions 303for `updating LPCXpresso firmware`_. 304 305Configuring a Console 306===================== 307 308Connect a USB cable from your PC to P6, and use the serial terminal of your choice 309(minicom, putty, etc.) with the following settings: 310 311- Speed: 115200 312- Data: 8 bits 313- Parity: None 314- Stop bits: 1 315 316Flashing 317======== 318 319Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the 320:ref:`linkserver-debug-host-tools` as default. 321 322.. zephyr-app-commands:: 323 :zephyr-app: samples/hello_world 324 :board: lpcxpresso55s69/lpc55s69/cpu0 325 :goals: flash 326 327Open a serial terminal, reset the board (press the RESET button), and you should 328see the following message in the terminal: 329 330.. code-block:: console 331 332 ***** Booting Zephyr OS v3.7.0 ***** 333 Hello World! lpcxpresso55s69/lpc55s69/cpu0 334 335Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| 336---------------------------------------------------------------------- 337The TF-M integration samples can be run using the 338``lpcxpresso55s69/lpc55s69/cpu0/ns`` target. To run we need to manually flash 339the resulting image (``tfm_merged.hex``) with a J-Link as follows 340(reset and erase are for recovering a locked core): 341 342 .. code-block:: console 343 344 JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1 345 J-Link>r 346 J-Link>erase 347 J-Link>loadfile build/zephyr/tfm_merged.hex 348 349We need to reset the board manually after flashing the image to run this code. 350 351Building a dual-core image 352-------------------------- 353The dual-core samples are run using ``lpcxpresso55s69/lpc55s69/cpu0`` target. 354Images built for ``lpcxpresso55s69/lpc55s69/cpu1`` will be loaded from flash 355and executed on the second core when ``SECOND_CORE_MCUX`` is selected. For 356an example of building for both cores with sysbuild, see 357``samples/subsys/ipc/openamp/`` 358 359Debugging 360========= 361 362Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the 363:ref:`jlink-debug-host-tools` as default. 364 365.. zephyr-app-commands:: 366 :zephyr-app: samples/hello_world 367 :board: lpcxpresso55s69/lpc55s69/cpu0 368 :goals: debug 369 370Open a serial terminal, step through the application in your debugger, and you 371should see the following message in the terminal: 372 373.. code-block:: console 374 375 ***** Booting Zephyr OS zephyr-v1.14.0 ***** 376 Hello World! lpcxpresso55s69 377 378.. _LPC55S69 SoC Website: 379 https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/high-efficiency-arm-cortex-m33-based-microcontroller-family:LPC55S6x 380 381.. _LPC55S69 Datasheet: 382 https://www.nxp.com/docs/en/nxp/data-sheets/LPC55S6x_DS.pdf 383 384.. _LPC55S69 Reference Manual: 385 https://www.nxp.com/webapp/Download?colCode=UM11126 386 387.. _LPCXPRESSO55S69 Website: 388 https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/lpcxpresso55s69-development-board:LPC55S69-EVK 389 390.. _LPCXPRESSO55S69 User Guide: 391 https://www.nxp.com/webapp/Download?colCode=UM11158 392 393.. _LPCXPRESSO55S69 Debug Firmware: 394 https://www.nxp.com/docs/en/application-note/AN13206.pdf 395 396.. _LPCXPRESSO55S69 Schematics: 397 https://www.nxp.com/webapp/Download?colCode=LPC55S69-SCH 398 399.. _updating LPCXpresso firmware: 400 https://os.mbed.com/teams/NXP/wiki/Updating-LPCXpresso-firmware 401
