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/Zephyr-latest/boards/technexion/pico_pi/doc/
Dindex.rst6 The i.MX7D SoC is a Hybrid multi-core processor composed of Single Cortex A7
9 communicate with the A7 core (running Linux) via RPmsg.
30 - CPU i.MX7 Dual with a Single Cortex A7 (1 GHz) core and
34 - RAM -> A7: 4GB
36 - Flash -> A7: 8GB eMMC
107 the A7 core. The A7 core is responsible to load the M4 binary application into
110 The A7 can perform these steps at bootloader level or after the Linux system
113 The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and
117 | Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
161 Below you will find the instructions to load and run Zephyr on M4 from A7 using
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/Zephyr-latest/scripts/coredump/gdbstubs/arch/
Dxtensa.py291 A7 = 96 variable in GdbRegDef_Sample_Controller.RegNum
325 A7 = 164 variable in GdbRegDef_ESP32.RegNum
357 A7 = 162 variable in GdbRegDef_ESP32S2.RegNum
387 A7 = 219 variable in GdbRegDef_ESP32S3.RegNum
428 A7 = 165 variable in GdbRegDef_Intel_Adsp_CAVS_Zephyr.RegNum
468 A7 = 263 variable in GdbRegDef_Intel_Adsp_CAVS_XCC.RegNum
503 A7 = 112 variable in GdbRegDef_DC233C.RegNum
Drisc_v.py34 A7 = 17 variable in RegNum
90 self.registers[RegNum.A7] = tu[12]
/Zephyr-latest/boards/element14/warp7/doc/
Dindex.rst6 The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7
9 communicate with the A7 core (running Linux) via RPmsg.
30 - Debug USB exposing two UARTs (UART1 for A7 and UART2 for M4)
38 - CPU i.MX7 Solo with a Single Cortex A7 (800MHz) core and
42 - RAM -> A7: 4GB (Kingston 08EMCP04)
44 - Flash -> A7: 8GB eMMC (Kingston 08EMCP04)
140 the A7 core. The A7 core is responsible to load the M4 binary application into
143 The A7 can perform these steps at bootloader level or after the Linux system
146 The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and
150 | Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
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/Zephyr-latest/boards/96boards/avenger96/doc/
Dindex.rst10 multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4
58 - 32-bit dual-core Arm® Cortex®-A7
127 - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)
194 on Cortex®-A7 core. Alternatively, Zephyr console output can be assigned to
204 started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the
206 The Cortex®-A7 can perform these steps at bootloader level or after the Linux
211 These are the memory mappings for Cortex®-A7 and Cortex®-M4:
214 | Region | Cortex®-A7 | Cortex®-M4 | Size |
232 environment. The firmware must first be loaded by the Cortex®-A7. Developer
/Zephyr-latest/boards/st/stm32mp157c_dk2/doc/
Dstm32mp157_dk2.rst7 multi-core processor,composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
14 - Arm®-based dual Cortex®-A7 32 bits
56 - 32-bit dual-core Arm® Cortex®-A7
130 - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)
205 by the Linux Remoteproc Framework on Cortex®-A7 core. In order to keep the UART7
215 started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the
217 The Cortex®-A7 can perform these steps at bootloader level or after the Linux
222 These are the memory mappings for Cortex®-A7 and Cortex®-M4:
225 | Region | Cortex®-A7 | Cortex®-M4 | Size |
243 environment. The firmware must first be loaded by the Cortex®-A7. Developer
/Zephyr-latest/boards/96boards/meerkat96/doc/
Dindex.rst10 composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
50 - Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core
55 - Internal RAM -> A7: 256KB SRAM
153 to be started by the A7 core. The A7 core is responsible to load the M4 binary
155 Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at
158 The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4:
161 | Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
205 A7 using u-boot.
/Zephyr-latest/boards/sparkfun/pro_micro_rp2040/
Dsparkfun_pro_micro_connector.dtsi20 , <6 0 &gpio0 6 0> /* D6/A7 */
/Zephyr-latest/boards/adafruit/kb2040/
Dsparkfun_pro_micro_connector.dtsi20 , <6 0 &gpio0 6 0> /* D6/A7 */
/Zephyr-latest/boards/st/nucleo_l031k6/
Darduino_nano_r3_connector.dtsi33 <21 0 &gpioa 2 0>; /* D21 / A7 */
/Zephyr-latest/boards/adafruit/nrf52_adafruit_feather/
Dfeather_connector.dtsi29 <16 0 &gpio0 31 0>, /* A7 (VBAT ADC) */
/Zephyr-latest/boards/enjoydigital/litex_vexriscv/doc/
Dindex.rst19 `Digilent Arty A7-35T or A7-100T Development Boards
47 bitstream for the FPGA on a Digilent Arty A7-35 Board or SDI-MIPI Video Converter. This can be achi…
70 …Generating the bitstream for the Digilent Arty A7-35 Board requires F4PGA toolchain installation. …
90 #. Set up the F4PGA environment (for the Digilent Arty A7-35 Board):
170 To upload the bitstream to Digilent Arty A7-35 you can use `xc3sprog <https://github.com/matrix-io/…
/Zephyr-latest/boards/digilent/arty_a7/
Darty_a7_designstart_fpga_cortex_m1.dts12 model = "Digilent Arty A7 ARM DesignStart Cortex-M1";
Darty_a7_designstart_fpga_cortex_m3.dts12 model = "Digilent Arty A7 ARM DesignStart Cortex-M3";
/Zephyr-latest/boards/seeed/wio_terminal/
Draspberrypi_40pins_connector.dtsi36 <24 0 &portb 7 0>, /* A7/D7 */
/Zephyr-latest/boards/st/nucleo_g031k8/
Darduino_nano_r3_connector.dtsi33 <21 0 &gpioa 7 0>; /* D21 / A7 */
/Zephyr-latest/boards/arduino/nano_33_iot/
Darduino_nano_r3_connector.dtsi33 <21 0 &portb 3 0>; /* D21 / A7 */
/Zephyr-latest/boards/arduino/nano_33_ble/
Darduino_nano_r3_connector.dtsi33 <21 0 &gpio1 3 0>; /* D21 / A7 */
/Zephyr-latest/boards/toradex/colibri_imx7d/doc/
Dindex.rst6 The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7
9 communicate with the A7 core (running Linux) via RPmsg.
14 - i.MX7 Single/Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core
18 - RAM -> A7: 256MB, 512MB and 1GB
20 - Flash -> A7: 4Gb eMMC and 512Mb NAND
129 the A7 core. The A7 core is responsible to load the M4 binary application into the
132 The A7 can perform these steps at bootloader level or after the Linux system has
135 The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4:
138 | Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
185 Below you will find the instructions to load and run Zephyr on M4 from A7 using u-boot.
/Zephyr-latest/boards/digilent/arty_a7/doc/
Dindex.rst19 :alt: Digilent Arty A7-35
21 Digilent Arty A7-35 (Credit: Digilent Inc)
138 Artix-35T FPGA. For other Arty variants (e.g. the Arty A7-100) the bitstream
/Zephyr-latest/boards/gaisler/generic_leon3/doc/
Dindex.rst14 designs such as the Digilent Arty A7, Terasic DE0-Nano and Microsemi
/Zephyr-latest/arch/sparc/core/
Dtrap_table_mvt.S177 SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A4 - A7
/Zephyr-latest/samples/tfm_integration/psa_crypto/
DREADME.rst275 00000060 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 ................
330 00000000 EE F1 FE A6 A8 41 5F CC A6 3A 73 A7 C1 33 B4 78 .....A_..:s..3.x
343 00000020 C0 92 12 97 4D D7 62 BC A0 0A 34 A7 CE A8 78 18 ....M.b...4...x.
/Zephyr-latest/samples/drivers/clock_control_litex/
DREADME.rst15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
/Zephyr-latest/boards/ti/cc1352p1_launchxl/doc/
Dindex.rst119 | DIO30 | AUX_IO | A7 |

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