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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/
Dxg22-pinctrl.h126 #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
127 #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
128 #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
129 #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
130 #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
131 #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
132 #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
133 #define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
136 #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
138 #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
[all …]
Dxg27-pinctrl.h132 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
141 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
144 #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
145 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
146 #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
147 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
148 #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
149 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
150 #define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6)
151 #define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7)
[all …]
Dxg24-pinctrl.h157 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
167 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
171 #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
172 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
173 #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
174 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
175 #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
176 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
177 #define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6)
178 #define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7)
[all …]
Dxg21-pinctrl.h112 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
119 #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
120 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
121 #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
122 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
123 #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
124 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
127 #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
133 #define ACMP1_ACMPOUT_PA2 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x2)
140 #define ACMP1_ACMPOUT_PC0 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x0)
[all …]
Dxg23-pinctrl.h174 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
185 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
190 #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
191 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
192 #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
193 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
194 #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
195 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
196 #define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6)
197 #define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7)
[all …]
/Zephyr-latest/arch/arm64/core/
Dearly_mem_funcs.S30 cmp x2, #8
39 sub x2, x2, #8
40 cmp x2, #7
45 cbz x2, 4f
48 subs x2, x2, #1
64 cmp x2, #8
69 sub x2, x2, #8
70 cmp x2, #7
75 cbz x2, 4f
79 subs x2, x2, #1
Dswitch.S57 lsr x2, x4, #TPIDRROEL0_EXC_SHIFT
63 orr x4, x4, x2, lsl #TPIDRROEL0_EXC_SHIFT
84 ldr x2, [x0, #_thread_offset_to_tls]
90 msr tpidr_el0, x2
114 ldr x2, [x0, #_thread_offset_to_stack_limit]
115 str x2, [x4, #_cpu_offset_to_current_stack_limit]
183 get_cpu x2
184 ldr w3, [x2, #___cpu_t_nested_OFFSET]
186 str w4, [x2, #___cpu_t_nested_OFFSET]
190 ldr x3, [x2, #___cpu_t_irq_stack_OFFSET]
[all …]
Dreset.S139 get_cpu_logic_id x1, x2, x3, x4 //x1: MPID, x2: logic id
145 strb w5, [x4, x2]
151 strb wzr, [x4, x2]
156 strb wzr, [x4, x2]
180 ldr x2, [x0, #BOOT_PARAM_MPID_OFFSET]
181 cmp x1, x2
/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dlsm6dsv16x.h18 #define LSM6DSV16X_DT_FS_500DPS 0x2
26 #define LSM6DSV16X_DT_ODR_AT_7Hz5 0x2
61 #define LSM6DSV16X_DT_XL_BATCHED_AT_7Hz5 0x2
76 #define LSM6DSV16X_DT_GY_BATCHED_AT_7Hz5 0x2
91 #define LSM6DSV16X_DT_TEMP_BATCHED_AT_15Hz 0x2
97 #define LSM6DSV16X_DT_SFLP_ODR_AT_60Hz 0x2
105 #define LSM6DSV16X_DT_SFLP_FIFO_GRAVITY 0x2
/Zephyr-latest/tests/drivers/gpio/gpio_reserved_ranges/boards/
Dnative_posix.overlay18 #gpio-cells = < 0x2 >;
30 #gpio-cells = < 0x2 >;
40 #gpio-cells = < 0x2 >;
51 #gpio-cells = < 0x2 >;
62 #gpio-cells = < 0x2 >;
73 #gpio-cells = < 0x2 >;
/Zephyr-latest/doc/services/pm/images/
Ddevr-async-ops.svg1 …x2="68" y1="36.2969" y2="468.6266"/><line style="stroke:#000000;stroke-width:1.0;stroke-dasharray:…
Ddevr-sync-ops.svg1 …x2="68" y1="36.2969" y2="455.961"/><line style="stroke:#000000;stroke-width:1.0;stroke-dasharray:5…
/Zephyr-latest/drivers/watchdog/
Dwdt_nxp_fs26.h72 #define FS26_M_STATUS (0x2)
133 #define VMON_PRE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_OV_FS_REACTION_SHIFT)
140 #define VMON_PRE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_UV_FS_REACTION_SHIFT)
147 #define VMON_CORE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_OV_FS_REACTION_SHIFT)
154 #define VMON_CORE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_UV_FS_REACTION_SHIFT)
161 #define VMON_LDO1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_OV_FS_REACTION_SHIFT)
168 #define VMON_LDO1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_UV_FS_REACTION_SHIFT)
175 #define VMON_LDO2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_OV_FS_REACTION_SHIFT)
182 #define VMON_LDO2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_UV_FS_REACTION_SHIFT)
191 #define VMON_EXT_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_OV_FS_REACTION_SHIFT)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Desp-pinctrl-common.h47 #define ESP32_PULL_UP 0x2
52 #define ESP32_OPEN_DRAIN 0x2
59 #define ESP32_PIN_OUT_LOW 0x2
66 #define ESP32_PIN_IN_EN 0x2
/Zephyr-latest/include/zephyr/posix/sys/
Dmman.h15 #define PROT_WRITE 0x2
19 #define MAP_PRIVATE 0x2
27 #define MS_INVALIDATE 0x2
/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma.yaml13 - 0x2: PERIPH to MEMORY
27 - 0x2: 32 bits
33 - 0x2: 32 bits
43 - 0x2: high
Dst,stm32u5-dma.yaml28 0x2: PERIPH to MEM
39 0x2: Word (32 bits)
44 0x2: Word (32 bits)
50 0x2: high
Dgd,gd32-dma-v1.yaml15 - 0x2: PERIPH to MEMORY
29 - 0x2: 32 bits
35 - 0x2: 32 bits
45 - 0x2: high
52 - 0x2: 3 word
Dst,stm32-dma-v1.yaml22 0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
33 0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
38 0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
46 0x2: hSTM32_DMA_PRIORITY_HIGH: high
52 0x2: STM32_DMA_FIFO_3_4: 3/4 full FIFO
Dst,stm32-dmamux.yaml18 0x2: PERIPH to MEM
29 0x2: Word (32 bits)
34 0x2: Word (32 bits)
42 0x2: high
/Zephyr-latest/tests/drivers/stepper/drv8424/emul/boards/
Dnative_sim.overlay29 #gpio-cells = <0x2>;
36 #gpio-cells = <0x2>;
43 #gpio-cells = <0x2>;
/Zephyr-latest/tests/drivers/stepper/drv8424/api/boards/
Dnative_sim.overlay29 #gpio-cells = <0x2>;
36 #gpio-cells = <0x2>;
43 #gpio-cells = <0x2>;
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx-alts-map.dtsi29 alts = <&scfg 0x01 0x2 0>;
55 alts = <&scfg 0x02 0x2 0>;
78 alts = <&scfg 0x03 0x2 0>;
98 alts = <&scfg 0x04 0x2 0>;
132 alts = <&scfg 0x06 0x2 0>;
158 alts = <&scfg 0x07 0x2 1>;
184 alts = <&scfg 0x08 0x2 1>;
210 alts = <&scfg 0x09 0x2 1>;
236 alts = <&scfg 0x0A 0x2 0>;
253 alts = <&scfg 0x0B 0x2 0>;
[all …]
/Zephyr-latest/include/zephyr/drivers/sensor/
Dwsen_hids_2525020210002.h30 hids_2525020210002_precision_High = 0x2
36 hids_2525020210002_heater_On_200mW_100ms = 0x2,
/Zephyr-latest/dts/arm/
Dcortex_r8_virt.dtsi47 interrupts = < 0x0 0x24 0x2 0xa0 >,
48 < 0x0 0x25 0x2 0xa0 >,
49 < 0x0 0x26 0x2 0xa0 >;

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