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Searched +full:write +full:- +full:fifo +full:- +full:depth (Results 1 – 21 of 21) sorted by relevance

/Zephyr-latest/dts/bindings/serial/
Daltr,jtag-uart.yaml3 compatible: "altr,jtag-uart"
5 include: uart-controller.yaml
11 write-fifo-depth:
15 Buffer size of transmit fifo. This used to implement irq_tx_complete.
16 Must be same as Write FIFO: Buffer depth (bytes) in platform designer.
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Ddmic_regs.h1 /* SPDX-License-Identifier: Apache-2.0 */
65 /* Common FIFO channels register (primary & secondary) (0000 - 0FFF)
72 /* Status Register for FIFO interface */
75 /* Data read/Write port for FIFO */
79 * (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
80 * (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count
81 * 001Ch - 00FFh Reserved space for extensions
149 #define OUTCONTROL_BFTH_MAX 4 /* Max depth 16 */
157 /* FIFO Initialize (FINIT): The software will set this bit to immediately clear FIFO pointers. */
163 /* Burst FIFO Threshold */
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/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Ddmic_regs.h1 /* SPDX-License-Identifier: Apache-2.0 */
42 /* Capture Link Select - select which link wall clock to time stamp. */
68 /* Common FIFO channels register (primary & secondary) (0000 - 0FFF)
75 /* Status Register for FIFO interface */
78 /* Data read/Write port for FIFO */
82 * (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
83 * (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count
84 * 001Ch - 00FFh Reserved space for extensions
152 #define OUTCONTROL_BFTH_MAX 4 /* Max depth 16 */
160 /* FIFO Initialize (FINIT): The software will set this bit to immediately clear FIFO pointers. */
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/Zephyr-latest/drivers/i2c/
Di2c_xilinx_axi.h1 /* SPDX-License-Identifier: Apache-2.0 */
22 REG_TX_FIFO = 0x108, /* Transmit FIFO */
23 REG_RX_FIFO = 0x10C, /* Receive FIFO */
25 REG_TX_FIFO_OCY = 0x114, /* Transmit FIFO Occupancy */
26 REG_RX_FIFO_OCY = 0x118, /* Receive FIFO Occupancy */
28 REG_RX_FIFO_PIRQ = 0x120, /* Receive FIFO Programmable Depth Interrupt */
48 ISR_TX_HALF_EMPTY = BIT(7), /* Transmit FIFO Half Empty */
52 ISR_RX_FIFO_FULL = BIT(3), /* Receive FIFO Full */
53 ISR_TX_FIFO_EMPTY = BIT(2), /* Transmit FIFO Empty */
70 CR_TX_FIFO_RST = BIT(1), /* Transmit FIFO Reset */
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Di2c_andes_atciic100.c4 * SPDX-License-Identifier: Apache-2.0
44 struct i2c_atciic100_dev_data_t *dev_data = dev->data; in i2c_atciic100_default_control()
47 k_sem_init(&dev_data->bus_lock, 1, 1); in i2c_atciic100_default_control()
48 k_sem_init(&dev_data->device_sync_sem, 0, 1); in i2c_atciic100_default_control()
56 /* I2C query FIFO depth */ in i2c_atciic100_default_control()
60 dev_data->fifo_depth = 2; in i2c_atciic100_default_control()
63 dev_data->fifo_depth = 4; in i2c_atciic100_default_control()
66 dev_data->fifo_depth = 8; in i2c_atciic100_default_control()
69 dev_data->fifo_depth = 16; in i2c_atciic100_default_control()
75 * 7-bit, CPU mode in i2c_atciic100_default_control()
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/Zephyr-latest/drivers/i3c/
Di3c_cdns.c4 * SPDX-License-Identifier: Apache-2.0
472 /* Target T_LOW period in open-drain mode. */
482 /* command response fifo threshold */
484 /* command tx fifo threshold - unused */
486 /* in-band-interrupt data fifo threshold - unused */
488 /* in-band-interrupt response queue threshold */
490 /* tx data threshold - unused */
504 /* The maxiumum command queue depth. */
506 /* The maxiumum command response queue depth. */
508 /* The maximum RX FIFO depth. */
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/Zephyr-latest/soc/ite/ec/common/
Dchip_chipregs.h3 * SPDX-License-Identifier: Apache-2.0
48 /* --- General Control (GCTRL) --- */
52 /* RISC-V JTAG Debug Interface Enable */
54 /* RISC-V JTAG Debug Interface Selection */
67 /* --- External GPIO Control (EGPIO) --- */
265 /* 0x049: PWM Output Open-Drain Enable */
280 /* --- Wake-Up Control (WUC) --- */
284 /* TODO: should a defined interface for configuring wake-up interrupts */
442 * 24-bit timers: external timer 3, 5, and 7
443 * 32-bit timers: external timer 4, 6, and 8
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/Zephyr-latest/drivers/dai/intel/dmic/
Ddmic.c4 * SPDX-License-Identifier: Apache-2.0
33 /* Helper macro to read 64-bit data using two 32-bit data read */
40 * fairly accurately exponent for x in range -2.0 .. +2.0. The iteration
61 p = num * x; /* Q9.23 x Q3.29 -> Q12.52 */ in exp_small_fixed()
79 if (x < Q_CONVERT_FLOAT(-11.5, 27)) { in exp_fixed()
110 if (db < Q_CONVERT_FLOAT(-100.0, 24)) { in db2lin_fixed()
122 uint32_t dest = dmic->reg_base + reg; in dai_dmic_update_bits()
130 sys_write32(val, dmic->reg_base + reg); in dai_dmic_write()
136 return sys_read32(dmic->reg_base + reg); in dai_dmic_read()
143 sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | in dai_dmic_claim_ownership()
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Ddmic_nhlt.c4 * SPDX-License-Identifier: Apache-2.0
29 sys_write32(val, dmic->reg_base + reg); in dai_dmic_write()
34 return sys_read32(dmic->reg_base + reg); in dai_dmic_read()
55 * @brief Write the fir coefficients in the PDMs' RAM
64 while (length--) { in dai_dmic_write_coeff()
71 while (length--) { in dai_dmic_write_coeff()
98 fir_length_a = FIELD_GET(FIR_CONFIG_FIR_LENGTH, pdm_cfg->fir_config[0].fir_config) + 1; in dai_dmic_configure_coeff()
99 fir_length_b = FIELD_GET(FIR_CONFIG_FIR_LENGTH, pdm_cfg->fir_config[1].fir_config) + 1; in dai_dmic_configure_coeff()
109 /* First dword is not included into length_0 and length_1 - skip it. */ in dai_dmic_configure_coeff()
118 if (dmic->dai_config_params.dai_index == 0) { in dai_dmic_configure_coeff()
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/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2.c4 * SPDX-License-Identifier: Apache-2.0
44 /* Minimum RX FIFO size in 32-bit words considering the largest used OUT packet
49 /* Default Rx FIFO size in 32-bit words calculated to support High-Speed with:
57 /* TX FIFO0 depth in 32-bit words (used by control IN endpoint)
63 /* Get Data FIFO access register */
105 /* Transfer triggers (IN on bits 0-15, OUT on bits 16-31) */
107 /* Finished transactions (IN on bits 0-15, OUT on bits 16-31) */
143 const struct udc_dwc2_config *const config = dev->config; in dwc2_init_pinctrl()
144 const struct pinctrl_dev_config *const pcfg = config->pcfg; in dwc2_init_pinctrl()
172 const struct udc_dwc2_config *const config = dev->config; in dwc2_get_base()
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/Zephyr-latest/include/zephyr/drivers/
Duart.h2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
69 * RS-485 half-duplex. This error is only valid on UARTs that
129 * @defgroup uart_interrupt Interrupt-driven UART API
161 * - Provide second buffer using uart_rx_buf_rsp, when first buffer is
163 * - Ignore the event, this way when current buffer is filled
214 * - When RX timeout occurred, and data was stored in provided buffer.
216 * - When provided buffer is full.
217 * - After uart_rx_disable().
218 * - After stopping due to external event (#UART_RX_STOPPED).
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/Zephyr-latest/drivers/usb/device/
Dusb_dc_dw.c5 * SPDX-License-Identifier: Apache-2.0
59 /* Number of SETUP back-to-back packets */
62 /* Get Data FIFO access register */
104 const struct pinctrl_dev_config *const pcfg = config->pcfg; in usb_dw_init_pinctrl()
189 "0x%x", base->gotgctl, base->gotgint, base->gahbcfg); in usb_dw_reg_dump()
191 base->gusbcfg, base->gintsts, base->gintmsk); in usb_dw_reg_dump()
193 base->dcfg, base->dctl, base->dsts); in usb_dw_reg_dump()
195 base->diepmsk, base->doepmsk, base->daint); in usb_dw_reg_dump()
197 base->daintmsk, base->ghwcfg1, base->ghwcfg2); in usb_dw_reg_dump()
199 base->ghwcfg3, base->ghwcfg4); in usb_dw_reg_dump()
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/Zephyr-latest/drivers/spi/
Dspi_pl022.c4 * SPDX-License-Identifier: Apache-2.0
110 /* TX FIFO empty */
112 /* TX FIFO not full */
114 /* RX FIFO not empty */
116 /* RX FIFO full */
145 /* Receive FIFO Interrupt mask */
147 /* Transmit FIFO Interrupt mask */
166 /* Receive FIFO Raw Interrupt status */
168 /* Transmit FIFO Raw Interrupt status */
187 /* Receive FIFO Masked Interrupt status */
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Dspi_smartbond.c4 * SPDX-License-Identifier: Apache-2.0
47 /* Bi-directional mode */
49 /* TX FIFO single depth, no flow control */
51 /* RX FIFO single depth, no flow control */
106 cfg->regs->SPI_CTRL_REG |= SPI_SPI_CTRL_REG_SPI_ON_Msk; in spi_smartbond_enable()
107 cfg->regs->SPI_CTRL_REG &= ~SPI_SPI_CTRL_REG_SPI_RST_Msk; in spi_smartbond_enable()
109 cfg->regs->SPI_CTRL_REG &= ~SPI_SPI_CTRL_REG_SPI_ON_Msk; in spi_smartbond_enable()
110 cfg->regs->SPI_CTRL_REG |= SPI_SPI_CTRL_REG_SPI_RST_Msk; in spi_smartbond_enable()
116 return (!!(cfg->regs->SPI_CTRL_REG & SPI_SPI_CTRL_REG_SPI_ON_Msk)) && in spi_smartbond_isenabled()
117 (!(cfg->regs->SPI_CTRL_REG & SPI_SPI_CTRL_REG_SPI_RST_Msk)); in spi_smartbond_isenabled()
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/Zephyr-latest/drivers/can/
Dcan_renesas_ra.c3 * SPDX-License-Identifier: Apache-2.0
60 * Common FIFO configuration: refer to '34.2.28 CFDCFCC : Common FIFO Configuration/Control
61 * Register' - RA8M1 MCU group HWM
63 #define CANFD_CFG_COMMONFIFO0 (0U << R_CANFD_CFDCFCC_CFE_Pos) /* Common FIFO Disable */
68 * RX FIFO configuration: refer to '34.2.25 CFDRFCCa : RX FIFO Configuration/Control Registers' -
72 ((1U << R_CANFD_CFDRFCC_RFE_Pos) | /* RX FIFO Enable */ \
73 (1U << R_CANFD_CFDRFCC_RFIE_Pos) | /* RX FIFO Interrupt Enable */ \
74 (7U << R_CANFD_CFDRFCC_RFPLS_Pos) | /* RX FIFO Payload Data Size: 64 */ \
75 (3U << R_CANFD_CFDRFCC_RFDC_Pos) | /* RX FIFO Depth: 16 messages */ \
80 #define CANFD_CFG_RX_FIFO1 (0U << R_CANFD_CFDRFCC_RFE_Pos) /* RX FIFO Disable */
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/Zephyr-latest/drivers/i2s/
Di2s_mcux_flexcomm.c4 * SPDX-License-Identifier: Apache-2.0
78 fsl_cfg->dataLength = i2s_cfg->word_size; in i2s_mcux_flexcomm_cfg_convert()
79 if ((i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) == in i2s_mcux_flexcomm_cfg_convert()
82 fsl_cfg->frameLength = 2 * i2s_cfg->word_size; in i2s_mcux_flexcomm_cfg_convert()
84 fsl_cfg->frameLength = i2s_cfg->channels * i2s_cfg->word_size; in i2s_mcux_flexcomm_cfg_convert()
87 if (fsl_cfg->dataLength < 4 || fsl_cfg->dataLength > 32) { in i2s_mcux_flexcomm_cfg_convert()
89 return -EINVAL; in i2s_mcux_flexcomm_cfg_convert()
92 if (fsl_cfg->frameLength < 4 || fsl_cfg->frameLength > 2048) { in i2s_mcux_flexcomm_cfg_convert()
94 return -EINVAL; in i2s_mcux_flexcomm_cfg_convert()
98 switch (i2s_cfg->options & (I2S_OPT_BIT_CLK_SLAVE | in i2s_mcux_flexcomm_cfg_convert()
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/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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Drelease-notes-2.3.rst18 with future support for features like 64-bit and absolute timeouts in mind
21 * Zephyr now integrates with the TF-M (Trusted Firmware M) PSA-compliant
24 * The CMSIS-DSP library is now included and integrated
33 * CVE-2020-10022: UpdateHub Module Copies a Variable-Sized Hash String
34 into a fixed-size array.
35 * CVE-2020-10059: UpdateHub Module Explicitly Disables TLS
37 * CVE-2020-10061: Improper handling of the full-buffer case in the
39 * CVE-2020-10062: Packet length decoding error in MQTT
40 * CVE-2020-10063: Remote Denial of Service in CoAP Option Parsing Due
42 * CVE-2020-10068: In the Zephyr project Bluetooth subsystem, certain
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Drelease-notes-2.6.rst13 * Added support for 64-bit ARCv3
14 * Split ARM32 and ARM64, ARM64 is now a top-level architecture
15 * Added initial support for Arm v8.1-m and Cortex-M55
22 https://github.com/zephyrproject-rtos/example-application
34 * CVE-2021-3581: Under embargo until 2021-09-04
41 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
46 * Driver APIs now return ``-ENOSYS`` if optional functions are not implemented.
47 If the feature is not supported by the hardware ``-ENOTSUP`` will be returned.
48 Formerly ``-ENOTSUP`` was returned for both failure modes, meaning this change
194 * Added support for null pointer dereferencing detection in Cortex-M.
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/Zephyr-latest/dts/common/nordic/
Dnrf9280.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/nrf-saadc.h>
10 #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h>
11 #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h>
12 #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h>
13 #include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h>
15 /delete-node/ &sw_pwm;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 #address-cells = <1>;
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Dnrf54h20.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/adc/nrf-saadc.h>
11 #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h>
12 #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h>
13 #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h>
14 #include <zephyr/dt-bindings/misc/nordic-tddconf.h>
15 #include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h>
16 #include <zephyr/dt-bindings/power/nordic-nrf-gpd.h>
18 /delete-node/ &sw_pwm;
21 #address-cells = <1>;
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