Lines Matching +full:write +full:- +full:fifo +full:- +full:depth
1 /* SPDX-License-Identifier: Apache-2.0 */
22 REG_TX_FIFO = 0x108, /* Transmit FIFO */
23 REG_RX_FIFO = 0x10C, /* Receive FIFO */
25 REG_TX_FIFO_OCY = 0x114, /* Transmit FIFO Occupancy */
26 REG_RX_FIFO_OCY = 0x118, /* Receive FIFO Occupancy */
28 REG_RX_FIFO_PIRQ = 0x120, /* Receive FIFO Programmable Depth Interrupt */
48 ISR_TX_HALF_EMPTY = BIT(7), /* Transmit FIFO Half Empty */
52 ISR_RX_FIFO_FULL = BIT(3), /* Receive FIFO Full */
53 ISR_TX_FIFO_EMPTY = BIT(2), /* Transmit FIFO Empty */
70 CR_TX_FIFO_RST = BIT(1), /* Transmit FIFO Reset */
76 SR_TX_FIFO_EMPTY = BIT(7), /* Transmit FIFO empty */
77 SR_RX_FIFO_EMPTY = BIT(6), /* Receive FIFO empty */
78 SR_RX_FIFO_FULL = BIT(5), /* Receive FIFO full */
79 SR_TX_FIFO_FULL = BIT(4), /* Transmit FIFO full */
80 SR_SRW = BIT(3), /* Target Read/Write */
86 /* TX FIFO */
92 /* RX FIFO */
109 /* Size of RX/TX FIFO */