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/Zephyr-latest/dts/bindings/display/panel/
Dpanel-timing.yaml2 # SPDX-License-Identifier: Apache-2.0
9 a panel under display-timings node. For example:
12 display-timings {
13 compatible = "zephyr,panel-timing";
14 hsync-len = <8>;
15 hfront-porch = <32>;
16 hback-porch = <32>;
17 vsync-len = <2>;
18 vfront-porch = <16>;
19 vback-porch = <14>;
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/Zephyr-latest/boards/shields/rk055hdmipi4ma0/
Drk055hdmipi4ma0.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 en_mipi_display_rk055hdmipi4ma0: enable-mipi-display-rk055hdmipi4ma0 {
16 compatible = "regulator-fixed";
17 regulator-name = "en_mipi_display";
18 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
19 regulator-boot-on;
23 compatible = "zephyr,lvgl-pointer-input";
30 gt911_rk055hdmipi4ma0: gt911-rk055hdmipi4ma0@5d {
33 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
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/Zephyr-latest/boards/shields/rk055hdmipi4m/
Drk055hdmipi4m.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 en_mipi_display: enable-mipi-display {
16 compatible = "regulator-fixed";
17 regulator-name = "en_mipi_display";
18 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
19 regulator-boot-on;
23 compatible = "zephyr,lvgl-pointer-input";
33 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
34 reset-gpios = <&nxp_mipi_connector 28 GPIO_ACTIVE_LOW>;
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/Zephyr-latest/boards/shields/rk043fn02h_ct/
Drk043fn02h_ct.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
16 compatible = "zephyr,lvgl-pointer-input";
26 int-gpios = <&nxp_i2c_touch_fpc 2 GPIO_ACTIVE_LOW>;
34 display-timings {
35 compatible = "zephyr,panel-timing";
36 hsync-len = <41>;
37 hfront-porch = <4>;
38 hback-porch = <8>;
39 vsync-len = <10>;
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/Zephyr-latest/boards/shields/rk043fn66hs_ctg/
Drk043fn66hs_ctg.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
16 compatible = "zephyr,lvgl-pointer-input";
26 irq-gpios = <&nxp_i2c_touch_fpc 2 GPIO_ACTIVE_HIGH>;
27 reset-gpios = <&nxp_i2c_touch_fpc 1 GPIO_ACTIVE_LOW>;
35 display-timings {
36 compatible = "zephyr,panel-timing";
37 hsync-len = <4>;
38 hfront-porch = <8>;
39 hback-porch = <43>;
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/Zephyr-latest/boards/shields/rtkmipilcdb00000be/
Drtkmipilcdb00000be.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 compatible = "zephyr,lvgl-pointer-input";
22 gt911_rtkmipilcdb00000be: gt911-rtkmipilcdb00000be@5d {
25 irq-gpios = <&renesas_mipi_connector 17 GPIO_ACTIVE_HIGH>;
26 reset-gpios = <&renesas_mipi_connector 18 GPIO_ACTIVE_LOW>;
34 compatible = "ilitek,ili9806e-dsi";
38 data-lanes = <2>;
39 pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
47 input-pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
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/Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/
Dst_b_lcd40_dsi1_mb1166.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
11 compatible = "zephyr,lvgl-pointer-input";
13 invert-y;
29 reset-gpios = <&dsi_lcd_qsh_030 57 GPIO_ACTIVE_HIGH>;
30 bl-gpios = <&dsi_lcd_qsh_030 53 GPIO_ACTIVE_HIGH>;
31 data-lanes = <2>;
32 pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
41 pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
43 display-timings {
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Dst_b_lcd40_dsi1_mb1166_a09.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
11 compatible = "zephyr,lvgl-pointer-input";
13 invert-y;
29 reset-gpios = <&dsi_lcd_qsh_030 57 GPIO_ACTIVE_HIGH>;
30 bl-gpios = <&dsi_lcd_qsh_030 53 GPIO_ACTIVE_HIGH>;
31 data-lanes = <2>;
32 pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
41 pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
43 display-timings {
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/Zephyr-latest/boards/renesas/da1469x_dk_pro/dts/
Dda1469x_dk_pro_lcdc.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
8 #include <zephyr/dt-bindings/display/panel.h>
19 swap-xy;
28 bias-pull-up;
36 bias-pull-up;
42 clock-frequency = <400000>;
49 int-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
55 pinctrl-0 = <&display_controller_default>;
56 pinctrl-1 = <&display_controller_sleep>;
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/Zephyr-latest/include/zephyr/drivers/
Dmipi_dsi.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public APIs for MIPI-DSI drivers
16 * @brief MIPI-DSI driver APIs
17 * @defgroup mipi_dsi_interface MIPI-DSI driver APIs
27 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
33 /** MIPI-DSI display timings. */
50 uint32_t vsync; member
54 * @name MIPI-DSI Device mode flags.
66 /** Enable hsync-end packets in vsync-pulse and v-porch area */
68 /** Disable hfront-porch area */
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Dmipi_dbi.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public APIs for MIPI-DBI drivers
11 * MIPI-DBI defines the following 3 interfaces:
25 * @brief MIPI-DBI driver APIs
26 * @defgroup mipi_dbi_interface MIPI-DBI driver APIs
37 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
152 /** MIPI-DBI host driver API */
156 const uint8_t *data, size_t len);
159 size_t num_cmds, uint8_t *response, size_t len);
186 * @param len size of data buffer in bytes. Set to 0 to skip sending data.
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/Zephyr-latest/boards/st/stm32f746g_disco/
Dstm32f746g_disco.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f7/stm32f746nghx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
17 compatible = "st,stm32f746g-disco";
21 zephyr,shell-uart = &usart1;
25 zephyr,flash-controller = &n25q128a1;
31 compatible = "gpio-leds";
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/Zephyr-latest/boards/st/stm32f429i_disc1/
Dstm32f429i_disc1.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include <st/f4/stm32f429zitx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/display/ili9xxx.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
20 zephyr,shell-uart = &usart1;
29 compatible = "zephyr,memory-region", "mmio-sram";
32 zephyr,memory-region = "SDRAM2";
36 compatible = "gpio-leds";
48 compatible = "gpio-keys";
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/Zephyr-latest/boards/st/stm32f7508_dk/
Dstm32f7508_dk.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include <st/f7/stm32f750n8hx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
16 model = "STMicroelectronics STM32F7508-DK";
21 zephyr,shell-uart = &usart1;
25 zephyr,flash-controller = &n25q128a1;
31 compatible = "gpio-leds";
39 compatible = "gpio-keys";
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/Zephyr-latest/boards/st/stm32h750b_dk/
Dstm32h750b_dk.dts2 * Copyright (c) 2023-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h750xbhx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "st,stm32h750b-dk";
19 zephyr,shell-uart = &usart3;
22 zephyr,flash-controller = &mt25ql512ab1;
27 compatible = "zephyr,memory-region", "mmio-sram";
30 zephyr,memory-region = "SDRAM2";
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/Zephyr-latest/boards/st/stm32h7b3i_dk/
Dstm32h7b3i_dk.dts2 * Copyright (c) 2022 Byte-Lab d.o.o. <dev@byte-lab.com>
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h7b3lihxq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
16 compatible = "st,stm32h7b3i-dk";
20 zephyr,shell-uart = &usart1;
29 compatible = "gpio-leds";
41 compatible = "gpio-keys";
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/Zephyr-latest/boards/witte/linum/
Dlinum.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h753bitx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
18 zephyr,shell-uart = &usart1;
22 zephyr,code-partition = &slot0_partition;
27 compatible = "zephyr,memory-region", "mmio-sram";
30 zephyr,memory-region = "SDRAM1";
31 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
35 compatible = "gpio-leds";
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/Zephyr-latest/drivers/mipi_dsi/
Ddsi_renesas_ra.c4 * SPDX-License-Identifier: Apache-2.0
70 const struct device *dev = (struct device *)p_args->p_context; in mipi_dsi_callback()
71 struct mipi_dsi_renesas_ra_data *data = dev->data; in mipi_dsi_callback()
73 switch (p_args->event) { in mipi_dsi_callback()
75 if (MIPI_DSI_SEQUENCE_STATUS_DESCRIPTORS_FINISHED == p_args->tx_status) { in mipi_dsi_callback()
76 data->message_sent = true; in mipi_dsi_callback()
81 data->fatal_error = true; in mipi_dsi_callback()
93 struct mipi_dsi_renesas_ra_data *data = dev->data; in mipi_dsi_renesas_ra_attach()
94 mipi_dsi_cfg_t cfg = data->mipi_dsi_cfg; in mipi_dsi_renesas_ra_attach()
97 if (!(mdev->mode_flags & MIPI_DSI_MODE_VIDEO)) { in mipi_dsi_renesas_ra_attach()
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Ddsi_stm32.c7 * SPDX-License-Identifier: Apache-2.0
61 const struct mipi_dsi_stm32_config *config = dev->config; in mipi_dsi_stm32_log_config()
62 struct mipi_dsi_stm32_data *data = dev->data; in mipi_dsi_stm32_log_config()
64 LOG_DBG("DISPLAY: pix %d kHz, lane %d kHz", data->pixel_clk_khz, data->lane_clk_khz); in mipi_dsi_stm32_log_config()
66 LOG_DBG(" AutomaticClockLaneControl 0x%x", data->hdsi.Init.AutomaticClockLaneControl); in mipi_dsi_stm32_log_config()
67 LOG_DBG(" TXEscapeCkdiv %u", data->hdsi.Init.TXEscapeCkdiv); in mipi_dsi_stm32_log_config()
68 LOG_DBG(" NumberOfLanes %u", data->hdsi.Init.NumberOfLanes); in mipi_dsi_stm32_log_config()
69 LOG_DBG(" PLLNDIV %u", data->pll_init.PLLNDIV); in mipi_dsi_stm32_log_config()
70 LOG_DBG(" PLLIDF %u", data->pll_init.PLLIDF); in mipi_dsi_stm32_log_config()
71 LOG_DBG(" PLLODF %u", data->pll_init.PLLODF); in mipi_dsi_stm32_log_config()
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/Zephyr-latest/drivers/mipi_dbi/
Dmipi_dbi_smartbond.c4 * SPDX-License-Identifier: Apache-2.0
100 struct mipi_dbi_smartbond_data *data = dev->data; in mipi_dbi_smartbond_send_single_frame()
108 k_sem_take(&data->sync_sem, K_FOREVER); in mipi_dbi_smartbond_send_single_frame()
111 LCDC->LCDC_INTERRUPT_REG |= LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk; in mipi_dbi_smartbond_send_single_frame()
114 LCDC->LCDC_MODE_REG |= LCDC_LCDC_MODE_REG_LCDC_SFRAME_UPD_Msk; in mipi_dbi_smartbond_send_single_frame()
117 k_sem_take(&data->sync_sem, K_FOREVER); in mipi_dbi_smartbond_send_single_frame()
119 if (data->underflow_flag) { in mipi_dbi_smartbond_send_single_frame()
121 data->underflow_flag = false; in mipi_dbi_smartbond_send_single_frame()
128 const struct mipi_dbi_smartbond_config *config = dev->config; in mipi_dbi_smartbond_reset()
131 if (!gpio_is_ready_dt(&config->reset)) { in mipi_dbi_smartbond_reset()
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/Zephyr-latest/drivers/display/
Ddisplay_nt35510.c4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/STMicroelectronics/stm32-nt35510/blob/main/nt35510.c
83 /* AVEE: -5.2V */
87 /* VCL: -2.5V */
97 /* VGL_REG: -10V */
103 /* VGMN/VGSN:-4.5V/0V */
105 /* VCOM: -1.325V */
156 static int nt35510_write_reg(const struct device *dev, uint8_t reg, const uint8_t *buf, size_t len) in nt35510_write_reg() argument
159 const struct nt35510_config *cfg = dev->config; in nt35510_write_reg()
161 ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, reg, buf, len); in nt35510_write_reg()
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Ddisplay_otm8009a.c5 * SPDX-License-Identifier: Apache-2.0
40 size_t len) in otm8009a_dcs_write() argument
42 const struct otm8009a_config *cfg = dev->config; in otm8009a_dcs_write()
45 ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, cmd, buf, len); in otm8009a_dcs_write()
54 static int otm8009a_mcs_write(const struct device *dev, uint16_t cmd, const void *buf, size_t len) in otm8009a_mcs_write() argument
56 const struct otm8009a_config *cfg = dev->config; in otm8009a_mcs_write()
61 ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, OTM8009A_MCS_ADRSFT, &scmd, 1); in otm8009a_mcs_write()
66 ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, cmd >> 8, buf, len); in otm8009a_mcs_write()
76 const struct otm8009a_config *cfg = dev->config; in otm8009a_check_id()
80 ret = mipi_dsi_dcs_read(cfg->mipi_dsi, cfg->channel, OTM8009A_CMD_ID1, &id, sizeof(id)); in otm8009a_check_id()
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Ddisplay_ili9806e_dsi.c4 * SPDX-License-Identifier: Apache-2.0
50 /* avdd +5.2v,avee-5.2v */
52 /* VGL=DDVDL+VCL-VCIP,VGH=2DDVDH-DDVDL */
210 static int ili9806e_write_reg(const struct device *dev, uint8_t reg, const uint8_t *buf, size_t len) in ili9806e_write_reg() argument
213 const struct ili9806e_config *cfg = dev->config; in ili9806e_write_reg()
215 ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, reg, buf, len); in ili9806e_write_reg()
236 ret = ili9806e_write_reg(dev, cmd->reg, cmd->cmd, cmd->cmd_len); in ili9806e_write_sequence()
238 LOG_ERR("Failed writing sequence: 0x%x result: (%d)", cmd->reg, ret); in ili9806e_write_sequence()
249 const struct ili9806e_config *cfg = dev->config; in ili9806e_config()
270 cfg->pixel_format == PIXEL_FORMAT_RGB_565 in ili9806e_config()
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