| /Zephyr-latest/drivers/spi/ |
| D | Kconfig | 1 # SPI driver configuration options
7 # SPI Drivers
9 menuconfig SPI config
10 bool "Serial Peripheral Interface (SPI) bus drivers"
12 Enable support for the SPI hardware bus.
14 if SPI
17 bool "SPI Shell"
20 Enable SPI Shell.
22 The currently SPI shell supports simple SPI write/read (transceive)
44 Enables Driver SPI slave operations. Slave support depends
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| D | spi_ll_stm32.h | 23 SPI_TypeDef *spi; member
75 static inline uint32_t ll_func_dma_get_reg_addr(SPI_TypeDef *spi, uint32_t location) in ll_func_dma_get_reg_addr() argument
80 return (uint32_t)&(spi->TXDR); in ll_func_dma_get_reg_addr()
83 return (uint32_t)&(spi->RXDR); in ll_func_dma_get_reg_addr()
86 return (uint32_t)LL_SPI_DMA_GetRegAddr(spi); in ll_func_dma_get_reg_addr()
90 /* checks that DMA Tx packet is fully transmitted over the SPI */
91 static inline uint32_t ll_func_spi_dma_busy(SPI_TypeDef *spi) in ll_func_spi_dma_busy() argument
94 return LL_SPI_IsActiveFlag_TXC(spi); in ll_func_spi_dma_busy()
96 /* the SPI Tx empty and busy flags are needed */ in ll_func_spi_dma_busy()
97 return (LL_SPI_IsActiveFlag_TXE(spi) && in ll_func_spi_dma_busy()
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| D | Kconfig.max32 | 5 bool "MAX32 MCU SPI controller driver"
10 Enable SPI support on the MAX32 family of processors.
15 bool "MAX32 MCU SPI Interrupt Support"
17 Enable interrupt support for MAX32 MCU SPI driver.
20 bool "MAX32 MCU SPI DMA Support"
24 Enable DMA support for MAX32 MCU SPI driver.
27 bool "MAX32 SPI RTIO Support"
35 default 8 # Sensible default that covers most common spi transactions
37 When RTIO is used with SPI, each driver holds a context with which blocking
38 API calls use to perform SPI transactions. This queue needs to be as deep
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| D | Kconfig.sam | 1 # Atmel SAM SPI
8 bool "Atmel SAM series SPI driver"
14 Enable support for the SAM SPI driver.
18 bool "SPI SAM DMA Support"
22 Enable using DMA with SPI for SPI instances that enable dma channels in
28 default 8 # Sensible default that covers most common spi transactions
30 When RTIO is use with SPI each driver holds a context with which blocking
31 API calls use to perform SPI transactions. This queue needs to be as deep
32 as the longest set of spi_buf_sets used, where normal SPI operations are
34 spi buffer sets for transmit/receive are not always matched equally in
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| D | spi_dw.c | 11 /* spi_dw.c - Designware SPI driver implementation */
33 #include <zephyr/drivers/spi.h>
34 #include <zephyr/drivers/spi/rtio.h>
44 static inline bool spi_dw_is_slave(struct spi_dw_data *spi) in spi_dw_is_slave() argument
47 spi_context_is_slave(&spi->ctx)); in spi_dw_is_slave()
52 struct spi_dw_data *spi = dev->data; in completed() local
53 struct spi_context *ctx = &spi->ctx; in completed()
59 if (spi_context_tx_on(&spi->ctx) || in completed()
60 spi_context_rx_on(&spi->ctx)) { in completed()
74 if (!spi_dw_is_slave(spi)) { in completed()
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| D | Kconfig.renesas_ra | 7 bool "Renesas RA SPI"
13 Enable Renesas RA SPI Driver.
18 bool "RA MCU SPI Interrupt Support"
20 Enable Interrupt support for the SPI Driver of RA family.
23 bool "RA MCU SPI DTC Support"
26 Enable the SPI DTC mode for SPI instances
29 bool "RA MCU SPI Hardware Slave Select support"
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| D | Kconfig.xmc4xxx | 5 bool "XMC4XX SPI driver"
11 Enable XMC4XXX SPI driver.
17 bool "XMC4XXX SPI interrupt mode"
19 Enables interrupt support for XMC4XXX SPI driver.
22 bool "XMC4XXX SPI DMA support"
25 Enables DMA for SPI transfers.
30 int "Timeout in milliseconds for an SPI transaction to complete if using DMA"
33 Sets timeout in milliseconds for an SPI transaction to complete when using DMA.
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| D | Kconfig.ambiq | 1 # Ambiq SDK SPI
10 bool "AMBIQ SPI Controller driver"
17 Enable driver for Ambiq SPI in Controller mode.
22 bool "AMBIQ APOLLO SPI DMA Support"
25 Enable DMA for Ambiq SPI.
37 bool "AMBIQ SPI Device driver"
44 Enable driver for Ambiq SPI in Device mode.
47 bool "AMBIQ SPI-BLEIF driver"
55 general IOM module) for SPI transceiver. It is always used for
61 bool "Ambiq SPI-BLEIF timing trace"
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| D | Kconfig.renesas_ra8 | 7 bool "Renesas RA SPI B"
13 Enable Renesas RA RA SPI B Driver.
18 bool "RA MCU SPI B Interrupt Support"
20 Enable Interrupt support for the SPI B Driver of RA family.
23 bool "RA MCU SPI DTC Support"
27 Enable the SPI DTC mode for SPI instances
30 bool "RA MCU SPI B Hardware Slave Select support"
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| D | Kconfig.mcux_lpspi | 1 # MCUXpresso SDK SPI
17 bool "MCUX LPSPI SPI DMA Support"
20 Enable the SPI DMA mode for SPI instances
26 default 8 # sensible default that covers most common spi transactions
28 when rtio is use with spi each driver holds a context with which blocking
29 api calls use to perform spi transactions. this queue needs to be as deep
30 as the longest set of spi_buf_sets used, where normal spi operations are
32 spi buffer sets for transmit/receive are not always matched equally in
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| /Zephyr-latest/tests/drivers/spi/spi_loopback/ |
| D | testcase.yaml | 2 depends_on: spi
5 - spi
7 filter: dt_compat_enabled("test-spi-loopback-slow") and
8 dt_compat_enabled("test-spi-loopback-fast")
13 drivers.spi.loopback: {}
14 drivers.spi.loopback.internal:
16 drivers.spi.loopback.lpspi.dma:
20 drivers.spi.loopback.lpspi.async.unset:
25 drivers.spi.loopback.lpspi.dma.async.unset:
30 drivers.spi.loopback.rtio:
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| /Zephyr-latest/soc/microchip/mec/ |
| D | Kconfig | 16 which generates an SPI image with TAG, Header, and firmware binary. This
18 Boot-ROM. Use the full Microchip SPI image generator program for
30 prompt "Clock rate to use for SPI flash"
33 This selects the SPI clock frequency that will be used for loading
37 bool "SPI flash clock rate of 12 MHz"
40 bool "SPI flash clock rate of 16 MHz"
43 bool "SPI flash clock rate of 24 MHz"
46 bool "SPI flash clock rate of 48 MHz"
58 prompt "Reading mode used by the SPI flash"
61 This sets the reading mode that can be used by the SPI flash.
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| /Zephyr-latest/include/zephyr/devicetree/ |
| D | spi.h | 3 * @brief SPI Devicetree macro public API header file.
20 * @defgroup devicetree-spi Devicetree SPI API
26 * @brief Does a SPI controller node have chip select GPIOs configured?
28 * SPI bus controllers use the "cs-gpios" property for configuring
34 * spi1: spi@... {
35 * compatible = "vnd,spi";
40 * spi2: spi@... {
41 * compatible = "vnd,spi";
49 * @param spi a SPI bus controller node identifier
50 * @return 1 if "spi" has a cs-gpios property, 0 otherwise
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| /Zephyr-latest/dts/bindings/led_strip/ |
| D | worldsemi,ws2812-spi.yaml | 5 Worldsemi WS2812 LED strip, SPI binding
8 strip with a SPI master.
10 The SPI driver should be usable as long as a zephyr SPI API driver
14 - spi-max-frequency
15 - spi-zero-frame
16 - spi-one-frame.
21 compatible: "worldsemi,ws2812-spi"
23 include: [spi-device.yaml, ws2812.yaml]
27 spi-one-frame:
30 description: 8-bit SPI frame to shift out for a 1 pulse.
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| /Zephyr-latest/soc/nuvoton/npcx/ |
| D | Kconfig | 44 prompt "Clock rate to use for SPI flash"
51 bool "SPI flash max clock rate of 20 MHz"
54 bool "SPI flash max clock rate of 25 MHz"
57 bool "SPI flash max clock rate of 33 MHz"
61 bool "SPI flash max clock rate of 40 MHz"
64 bool "SPI flash max clock rate of 50 MHz"
76 prompt "Reading mode used by the SPI flash"
79 This sets the reading mode that can be used by the SPI flash.
83 bool "SPI flash operates with normal reading mode"
86 bool "SPI flash operates with fast reading mode"
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| /Zephyr-latest/dts/bindings/spi/ |
| D | spi-device.yaml | 4 # Common fields for SPI devices
8 on-bus: spi
13 spi-max-frequency:
16 description: Maximum clock frequency of device's SPI interface in Hz
24 list (see dt-bindings/spi/spi.h)
37 list (see dt-bindings/spi/spi.h)
43 spi-cpol:
46 SPI clock polarity which indicates the clock idle state.
48 spi-cpha:
51 SPI clock phase that indicates on which edge data is sampled.
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| D | nordic,nrf-spi-common.yaml | 4 # Common fields for Nordic nRF family SPI peripherals
6 include: [spi-controller.yaml, pinctrl-device.yaml, nordic-clockpin.yaml]
25 Maximum data rate the SPI peripheral can be driven at, in Hz. This
32 in SPI transfers.
44 Optional bi-directional line that allows SPI master to indicate to SPI
50 - initially, SPI slave configures its WAKE line pin as an input and SPI
52 - when a transfer is to be performed, SPI master configures its WAKE
54 high but allows SPI slave to override that state
55 - when SPI slave detects the high state of the WAKE line, it prepares
59 to SPI master that it can proceed with the transfer
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| /Zephyr-latest/samples/drivers/spi_flash_at45/ |
| D | sample.yaml | 2 name: SPI Flash AT45 Sample
4 sample.drivers.spi.flash.at45.build:
6 - spi
8 depends_on: spi
11 sample.drivers.spi.flash.at45.build.page_layout:
14 - spi
16 depends_on: spi
19 sample.drivers.spi.flash.at45.build.pm:
22 - spi
24 depends_on: spi
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| /Zephyr-latest/dts/bindings/memory-controllers/ |
| D | renesas,smartbond-nor-psram.yaml | 102 - "spi-mode0"
103 - "spi-mode3"
104 default: "spi-mode0"
170 - "single-spi"
171 - "dual-spi"
172 - "quad-spi"
173 default: "single-spi"
175 Describes the mode of SPI bus during the address phase for single/burst
182 - "single-spi"
183 - "dual-spi"
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| /Zephyr-latest/dts/bindings/mipi-dbi/ |
| D | mipi-dbi-spi-device.yaml | 4 # Common fields for MIPI DBI devices using Mode C (SPI)
13 SPI Duplex mode, full or half. By default it's always full duplex thus 0
15 Selecting half duplex allows to use SPI MOSI as a bidirectional line,
18 list (see dt-bindings/spi/spi.h)
24 SPI clock polarity which indicates the clock idle state.
29 SPI clock phase that indicates on which edge data is sampled.
34 In some cases, it is necessary for the master to manage SPI chip select
35 under software control, so that multiple spi transactions can be performed
36 without releasing it. A typical use case is variable length SPI packets
37 where the first spi transaction reads the length and the second spi transaction
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| /Zephyr-latest/tests/drivers/build_all/sensor/ |
| D | spi.dtsi | 6 * Application overlay for spi devices
16 spi-max-frequency = <0>;
23 spi-max-frequency = <0>;
30 spi-max-frequency = <0>;
36 spi-max-frequency = <0>;
43 spi-max-frequency = <0>;
49 spi-max-frequency = <0>;
56 spi-max-frequency = <0>;
63 spi-max-frequency = <0>;
70 spi-max-frequency = <0>;
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| /Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/ |
| D | ec_host_cmd_backend_spi_stm32.c | 7 /* The SPI STM32 backend implements dedicated SPI driver for Host Commands. Unfortunately, the
8 * current SPI API can't be used to handle the host commands communication. The main issues are
9 * unknown command size sent by the host (the SPI transaction sends/receives specific number of
10 * bytes) and need to constant sending status byte (the SPI module is enabled and disabled per
23 #include <zephyr/drivers/spi.h>
32 /* The default compatible string of a SPI devicetree node has to be replaced with the one
33 * dedicated for Host Commands. It disabled standard SPI driver. For STM32 SPI "st,stm32-spi" has
34 * to be changed to "st,stm32-spi-host-cmd". The remaining "additional" compatible strings should
39 "The chosen backend node is obligatory for SPI STM32 backend.");
42 "Invalid compatible of the chosen spi node.");
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| /Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/ |
| D | testcase.yaml | 2 depends_on: spi
5 - spi
17 drivers.spi.spi_mode0:
24 drivers.spi.spi_mode1:
31 drivers.spi.spi_mode2:
38 drivers.spi.spi_mode3:
45 drivers.spi.spi_4MHz:
52 drivers.spi.spi_8MHz:
59 drivers.spi.spi_fast:
67 drivers.spi.pm_runtime:
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| /Zephyr-latest/doc/services/device_mgmt/ |
| D | ec_host_cmd.rst | 39 Another case is SPI. Unfortunately, the current SPI API can't be used to handle the host commands
40 communication. The main issues are unknown command size sent by the host (the SPI transaction
41 sends/receives specific number of bytes) and need to constant sending status byte (the SPI module
42 is enabled and disabled per transaction). It forces implementing the SPI driver within a backend,
43 as it is done for SHI. That means a SPI backend has to be implemented per chip family. However, it
44 can be changed in the future once the SPI API is extended to host command needs. Please check `the
47 That approach requires configuring the SPI dts node in a special way. The main compatible string of
48 a SPI node has changed to use the Host Command version of a SPI driver. The rest of the properties
49 should be configured as usual. Example of the SPI node for STM32:
55 * STM32 SPI driver
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| /Zephyr-latest/tests/drivers/spi/dt_spec/ |
| D | app.overlay | 22 test_spi_cs: spi@33334444 {
25 compatible = "vnd,spi";
32 test_spi_dev_cs: test-spi-dev@0 {
33 compatible = "vnd,spi-device";
35 spi-max-frequency = <2000000>;
39 test_spi_no_cs: spi@55556666 {
42 compatible = "vnd,spi";
47 test_spi_dev_no_cs: test-spi-dev@0 {
48 compatible = "vnd,spi-device";
50 spi-max-frequency = <2000000>;
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