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/Zephyr-latest/soc/microchip/mec/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
7 if SOC_FAMILY_MICROCHIP_MEC
16 which generates an SPI image with TAG, Header, and firmware binary. This
18 Boot-ROM. Use the full Microchip SPI image generator program for
19 authentication and all other Boot-ROM loader features. Refer to the MCHP
22 if MCHP_MEC_UNSIGNED_HEADER
26 default "mec15xx" if SOC_SERIES_MEC15XX
27 default "mec172x" if SOC_SERIES_MEC172X
30 prompt "Clock rate to use for SPI flash"
33 This selects the SPI clock frequency that will be used for loading
[all …]
/Zephyr-latest/drivers/spi/
Dspi_ll_stm32.h4 * SPDX-License-Identifier: Apache-2.0
14 /* This symbol takes the value 1 if one of the device instances */
16 #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
23 SPI_TypeDef *spi; member
28 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_spi_subghz)
31 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
75 static inline uint32_t ll_func_dma_get_reg_addr(SPI_TypeDef *spi, uint32_t location) in ll_func_dma_get_reg_addr() argument
77 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) in ll_func_dma_get_reg_addr()
78 if (location == SPI_STM32_DMA_TX) { in ll_func_dma_get_reg_addr()
80 return (uint32_t)&(spi->TXDR); in ll_func_dma_get_reg_addr()
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Dspi_dw.c6 * SPDX-License-Identifier: Apache-2.0
11 /* spi_dw.c - Designware SPI driver implementation */
33 #include <zephyr/drivers/spi.h>
34 #include <zephyr/drivers/spi/rtio.h>
44 static inline bool spi_dw_is_slave(struct spi_dw_data *spi) in spi_dw_is_slave() argument
47 spi_context_is_slave(&spi->ctx)); in spi_dw_is_slave()
52 struct spi_dw_data *spi = dev->data; in completed() local
53 struct spi_context *ctx = &spi->ctx; in completed()
55 if (error) { in completed()
59 if (spi_context_tx_on(&spi->ctx) || in completed()
[all …]
Dspi_ll_stm32.c4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/drivers/spi.h>
19 #include <zephyr/drivers/spi/rtio.h>
35 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
39 #include <zephyr/linker/linker-defs.h>
46 #if defined(CONFIG_DCACHE) && \
61 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
65 #if defined(LL_SPI_SR_UDR)
78 if (IS_ENABLED(CONFIG_PM)) { in spi_stm32_pm_policy_state_lock_get()
79 struct spi_stm32_data *data = dev->data; in spi_stm32_pm_policy_state_lock_get()
[all …]
Dspi_pw.c3 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/drivers/spi.h>
13 #include <zephyr/drivers/spi/rtio.h>
15 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
45 static bool is_spi_transfer_ongoing(struct spi_pw_data *spi) in is_spi_transfer_ongoing() argument
47 return spi_context_tx_on(&spi->ctx) || spi_context_rx_on(&spi->ctx); in is_spi_transfer_ongoing()
69 if (enable) { in spi_pw_cs_sw_ctrl()
84 if (rx_mask) { in spi_pw_intr_enable()
132 uint8_t dfs = SPI_WORD_SIZE_GET(config->operation); in spi_pw_get_frame_size()
136 if ((dfs == 0) || (dfs > PW_SPI_FRAME_SIZE_4_BYTES)) { in spi_pw_get_frame_size()
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DKconfig.max322 # SPDX-License-Identifier: Apache-2.0
5 bool "MAX32 MCU SPI controller driver"
10 Enable SPI support on the MAX32 family of processors.
12 if SPI_MAX32
15 bool "MAX32 MCU SPI Interrupt Support"
17 Enable interrupt support for MAX32 MCU SPI driver.
20 bool "MAX32 MCU SPI DMA Support"
22 select CACHE_MANAGEMENT if CPU_HAS_DCACHE
24 Enable DMA support for MAX32 MCU SPI driver.
27 bool "MAX32 SPI RTIO Support"
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Dspi_sedi.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/spi.h>
11 #include <zephyr/drivers/spi/rtio.h>
40 struct spi_sedi_data *data = dev->data; in spi_sedi_configure()
41 const struct spi_sedi_config *info = dev->config; in spi_sedi_configure()
44 if (spi_context_configured(&data->ctx, config) == true) { in spi_sedi_configure()
48 word_size = SPI_WORD_SIZE_GET(config->operation); in spi_sedi_configure()
49 sedi_spi_control(info->spi_device, SEDI_SPI_IOCTL_DATA_WIDTH, in spi_sedi_configure()
53 cpol = SPI_MODE_GET(config->operation) & SPI_MODE_CPOL; in spi_sedi_configure()
54 cpha = SPI_MODE_GET(config->operation) & SPI_MODE_CPHA; in spi_sedi_configure()
[all …]
DKconfig.xmc4xxx2 # SPDX-License-Identifier: Apache-2.0
5 bool "XMC4XX SPI driver"
11 Enable XMC4XXX SPI driver.
14 if SPI_XMC4XXX
17 bool "XMC4XXX SPI interrupt mode"
19 Enables interrupt support for XMC4XXX SPI driver.
22 bool "XMC4XXX SPI DMA support"
25 Enables DMA for SPI transfers.
27 if SPI_XMC4XXX_DMA
30 int "Timeout in milliseconds for an SPI transaction to complete if using DMA"
[all …]
Dspi_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/drivers/spi.h>
18 #include <zephyr/drivers/spi/rtio.h>
37 XMC_USIC_CH_t *spi; member
40 #if defined(CONFIG_SPI_XMC4XXX_INTERRUPT)
43 #if defined(CONFIG_SPI_XMC4XXX_DMA)
60 #if defined(CONFIG_SPI_XMC4XXX_DMA)
71 #if defined(CONFIG_SPI_XMC4XXX_DMA)
77 if (status != 0) { in spi_xmc4xxx_dma_callback()
79 data->dma_status_flags |= SPI_XMC4XXX_DMA_ERROR_FLAG; in spi_xmc4xxx_dma_callback()
[all …]
DKconfig.sam1 # Atmel SAM SPI
5 # SPDX-License-Identifier: Apache-2.0
8 bool "Atmel SAM series SPI driver"
14 Enable support for the SAM SPI driver.
16 if SPI_SAM
18 bool "SPI SAM DMA Support"
19 default y if SPI_RTIO
22 Enable using DMA with SPI for SPI instances that enable dma channels in
25 if SPI_RTIO
28 default 8 # Sensible default that covers most common spi transactions
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Dspi_numaker.c2 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/spi/rtio.h>
26 SPI_T *spi; member
42 * CPOL/CPHA = 0/0 --> SPI_MODE_0
43 * CPOL/CPHA = 0/1 --> SPI_MODE_1
44 * CPOL/CPHA = 1/0 --> SPI_MODE_2
45 * CPOL/CPHA = 1/1 --> SPI_MODE_3
58 struct spi_numaker_data *data = dev->data; in spi_numaker_configure()
59 const struct spi_numaker_config *dev_cfg = dev->config; in spi_numaker_configure()
62 if (spi_context_configured(&data->ctx, config)) { in spi_numaker_configure()
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DKconfig.nrfx1 # Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
2 # SPDX-License-Identifier: Apache-2.0
5 bool "nRF SPI nrfx drivers"
11 Enable support for nrfx SPI drivers for nRF MCU series.
13 if SPI_NRFX
18 select NRFX_SPI0 if HAS_HW_NRF_SPI0
19 select NRFX_SPI1 if HAS_HW_NRF_SPI1
20 select NRFX_SPI2 if HAS_HW_NRF_SPI2
25 select NRFX_SPIM0 if HAS_HW_NRF_SPIM0
26 select NRFX_SPIM1 if HAS_HW_NRF_SPIM1
[all …]
DKconfig.gd322 # SPDX-License-Identifier: Apache-2.0
5 bool "Gigadevice GD32 SPI driver"
10 Enables Gigadevice GD32 SPI driver.
12 if SPI_GD32
15 bool "GD32 MCU SPI Interrupt Support"
16 default y if SPI_ASYNC
17 default y if SPI_GD32_DMA
19 Enable the interrupt driven mode for SPI instances
22 bool "GD32 MCU SPI DMA Support"
26 Use the DMA for SPI transfer
Dspi_nrfx_spi.c2 * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/drivers/spi.h>
8 #include <zephyr/drivers/spi/rtio.h>
30 nrfx_spi_t spi; member
44 if (frequency < 250000) { in get_nrf_spi_frequency()
46 } else if (frequency < 500000) { in get_nrf_spi_frequency()
48 } else if (frequency < 1000000) { in get_nrf_spi_frequency()
50 } else if (frequency < 2000000) { in get_nrf_spi_frequency()
52 } else if (frequency < 4000000) { in get_nrf_spi_frequency()
[all …]
DKconfig.stm321 # STM32 SPI driver configuration options
3 # Copyright (c) 2015-2016 Intel Corporation
4 # SPDX-License-Identifier: Apache-2.0
7 bool "STM32 MCU SPI controller driver"
13 Enable SPI support on the STM32 family of processors.
15 if SPI_STM32
18 bool "STM32 MCU SPI Interrupt Support"
20 Enable Interrupt support for the SPI Driver of STM32 family.
23 bool "STM32 MCU SPI DMA Support"
25 select CACHE_MANAGEMENT if CPU_HAS_DCACHE
[all …]
/Zephyr-latest/soc/nuvoton/npcx/
DKconfig1 # Nuvoton Cortex-M4 Embedded Controller
4 # SPDX-License-Identifier: Apache-2.0
6 if SOC_FAMILY_NPCX
15 if NPCX_HEADER
34 default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC
35 default "npcx7m7" if SOC_NPCX7M7FC
36 default "npcx9m3" if SOC_NPCX9M3F
37 default "npcx9m6" if SOC_NPCX9M6F
38 default "npcx9m7" if SOC_NPCX9M7F || SOC_NPCX9M7FB
39 default "npcx9mfp" if SOC_NPCX9MFP
[all …]
/Zephyr-latest/drivers/sensor/tdk/icm42605/
Dicm42605_setup.c4 * SPDX-License-Identifier: Apache-2.0
19 const struct icm42605_config *cfg = dev->config; in icm42605_set_fs()
23 result = inv_spi_read(&cfg->spi, REG_ACCEL_CONFIG0, &databuf, 1); in icm42605_set_fs()
24 if (result) { in icm42605_set_fs()
31 result = inv_spi_single_write(&cfg->spi, REG_ACCEL_CONFIG0, &databuf); in icm42605_set_fs()
33 result = inv_spi_read(&cfg->spi, REG_GYRO_CONFIG0, &databuf, 1); in icm42605_set_fs()
35 if (result) { in icm42605_set_fs()
42 result = inv_spi_single_write(&cfg->spi, REG_GYRO_CONFIG0, &databuf); in icm42605_set_fs()
44 if (result) { in icm42605_set_fs()
53 const struct icm42605_config *cfg = dev->config; in icm42605_set_odr()
[all …]
/Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/
Dec_host_cmd_backend_spi_stm32.c4 * SPDX-License-Identifier: Apache-2.0
7 /* The SPI STM32 backend implements dedicated SPI driver for Host Commands. Unfortunately, the
8 * current SPI API can't be used to handle the host commands communication. The main issues are
9 * unknown command size sent by the host (the SPI transaction sends/receives specific number of
10 * bytes) and need to constant sending status byte (the SPI module is enabled and disabled per
11 * transaction), see https://github.com/zephyrproject-rtos/zephyr/issues/56091.
23 #include <zephyr/drivers/spi.h>
32 /* The default compatible string of a SPI devicetree node has to be replaced with the one
33 * dedicated for Host Commands. It disabled standard SPI driver. For STM32 SPI "st,stm32-spi" has
34 * to be changed to "st,stm32-spi-host-cmd". The remaining "additional" compatible strings should
[all …]
/Zephyr-latest/samples/drivers/spi_fujitsu_fram/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/spi.h>
14 * @file Sample app using the Fujitsu MB85RS64V FRAM through SPI.
25 static int mb85rs64v_access(const struct device *spi, in mb85rs64v_access() argument
45 if (cmd == MB85RS64V_WRITE_CMD || cmd == MB85RS64V_READ_CMD) { in mb85rs64v_access()
52 if (cmd == MB85RS64V_READ_CMD) { in mb85rs64v_access()
58 return spi_transceive(spi, spi_cfg, &tx, &rx); in mb85rs64v_access()
64 return spi_write(spi, spi_cfg, &tx); in mb85rs64v_access()
68 static int mb85rs64v_read_id(const struct device *spi, in mb85rs64v_read_id() argument
74 err = mb85rs64v_access(spi, spi_cfg, in mb85rs64v_read_id()
[all …]
/Zephyr-latest/dts/bindings/spi/
Dnxp,s32-spi.yaml1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP S32 SPI controller
6 compatible: "nxp,s32-spi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
17 num-cs:
26 pinctrl-0:
29 pinctrl-names:
35 Select if the SPI module is intended to be used in slave mode.
37 spi-sck-cs-delay:
[all …]
/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,smartbond-nor-psram.yaml2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "renesas,smartbond-nor-psram"
14 is-ram:
17 If present, the memory controller will be configured to drive PSRAM devices.
19 dev-size:
25 dev-type:
31 dev-density:
40 dev-id:
46 reset-delay-us:
52 read-cs-idle-min-ns:
[all …]
/Zephyr-latest/soc/espressif/common/
DKconfig.spiram2 # SPDX-License-Identifier: Apache-2.0
4 if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
7 bool "Support for external, SPI-connected RAM"
8 default n if MCUBOOT
9 default n if ESP32_USE_UNSUPPORTED_REVISION && SOC_SERIES_ESP32
12 This enables support for an external SPI RAM chip, connected in
13 parallel with the main SPI flash chip.
15 menu "SPI RAM config"
23 regions. If the region of desired capability is exhausted,
28 default 262134 if SYS_HEAP_SMALL_ONLY
[all …]
/Zephyr-latest/include/zephyr/devicetree/
Dspi.h3 * @brief SPI Devicetree macro public API header file.
9 * SPDX-License-Identifier: Apache-2.0
20 * @defgroup devicetree-spi Devicetree SPI API
26 * @brief Does a SPI controller node have chip select GPIOs configured?
28 * SPI bus controllers use the "cs-gpios" property for configuring
29 * chip select GPIOs. Its value is a phandle-array which specifies the
34 * spi1: spi@... {
35 * compatible = "vnd,spi";
36 * cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
40 * spi2: spi@... {
[all …]
/Zephyr-latest/drivers/wifi/eswifi/
Deswifi_bus_spi.c4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/drivers/spi.h>
44 static bool eswifi_spi_cmddata_ready(struct eswifi_spi_data *spi) in eswifi_spi_cmddata_ready() argument
46 return gpio_pin_get_dt(&spi->cfg->dr) > 0; in eswifi_spi_cmddata_ready()
49 static int eswifi_spi_wait_cmddata_ready(struct eswifi_spi_data *spi) in eswifi_spi_wait_cmddata_ready() argument
56 } while (!eswifi_spi_cmddata_ready(spi) && --max_retries); in eswifi_spi_wait_cmddata_ready()
58 return max_retries ? 0 : -ETIMEDOUT; in eswifi_spi_wait_cmddata_ready()
63 struct eswifi_spi_data *spi = eswifi->bus_data; in eswifi_spi_write() local
73 status = spi_write_dt(&spi->cfg->bus, &spi_tx); in eswifi_spi_write()
74 if (status) { in eswifi_spi_write()
[all …]
/Zephyr-latest/drivers/sensor/tdk/icm42688/
Dicm42688_common.c6 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/spi.h>
24 const struct icm42688_dev_cfg *dev_cfg = dev->config; in icm42688_reset()
29 /* perform a soft reset to ensure a clean slate, reset bit will auto-clear */ in icm42688_reset()
30 res = icm42688_spi_single_write(&dev_cfg->spi, REG_DEVICE_CONFIG, BIT_SOFT_RESET); in icm42688_reset()
32 if (res) { in icm42688_reset()
41 res = icm42688_spi_read(&dev_cfg->spi, REG_INT_STATUS, &value, 1); in icm42688_reset()
43 if (res) { in icm42688_reset()
47 if (FIELD_GET(BIT_INT_STATUS_RESET_DONE, value) != 1) { in icm42688_reset()
49 return -EINVAL; in icm42688_reset()
[all …]

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