Home
last modified time | relevance | path

Searched +full:single +full:- +full:lane (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/dts/bindings/usb-c/
Dusb-c-connector.yaml2 # SPDX-License-Identifier: Apache-2.0
5 A USB Type-C connector node represents a physical USB Type-C connector.
6 It should be a child of a USB-C interface controller or a separate node
7 when it is attached to both MUX and USB-C interface controller.
10 …/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/connector/usb-connector.yaml?h=v5.1…
14 USB-C connector attached to a STM32 UCPD typec port controller, which has
18 compatible = "zephyr,usb-c-vbus-adc";
19 io-channels = <&adc2 8>;
20 output-ohms = <49900>;
21 full-ohms = <(330000 + 49900)>;
[all …]
/Zephyr-latest/boards/nxp/imx95_evk/doc/
Dindex.rst6 The i.MX95 EVK (IMX95LPD5EVK-19) board is a platform designed to show the
8 It is an entry-level development board, which helps developers to get familiar
16 - i.MX 95 automotive applications processor
18 - The processor integrates up to six Arm Cortex-A55 cores, and supports
19 functional safety with built-in Arm Cortex-M33 and -M7 cores
21 - DRAM memory: 128-Gbit LPDDR5 DRAM
22 - eMMC: 64 GB Micron eMMC
23 - SPI NOR flash memory: 1 Gbit octal flash memory
24 - USB interface: Two USB ports: Type-A and Type-C
25 - Audio codec interface
[all …]
/Zephyr-latest/include/zephyr/drivers/pcie/
Dcap.h4 * SPDX-License-Identifier: Apache-2.0
30 #define PCI_CAP_ID_PCIX 0x07U /**< PCI-X */
32 #define PCI_CAP_ID_VNDR 0x09U /**< Vendor-Specific */
35 #define PCI_CAP_ID_SHPC 0x0CU /**< PCI Standard Hot-Plug Controller */
40 #define PCI_CAP_ID_MSIX 0x11U /**< MSI-X */
62 #define PCIE_EXT_CAP_ID_MFVC 0x0008U /**< Multi-Function VC Capability */
65 #define PCIE_EXT_CAP_ID_VNDR 0x000BU /**< Vendor-Specific Extended Capability */
66 #define PCIE_EXT_CAP_ID_CAC 0x000CU /**< Config Access Correlation - obsolete */
68 #define PCIE_EXT_CAP_ID_ARI 0x000EU /**< Alternate Routing-ID Interpretation */
70 #define PCIE_EXT_CAP_ID_SRIOV 0x0010U /**< Single Root I/O Virtualization */
[all …]
/Zephyr-latest/boards/nxp/ls1046ardb/doc/
Dindex.rst6 The LS1046A reference design board (RDB) is a high-performance computing,
10 of high-speed SerDes ports.
12 The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72
13 cores with packet processing acceleration and high-speed peripherals. The
25 - Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed
26 - Supports 8 GB DDR4 SDRAM memory
27 - SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi
29 - One 512 MB SLC NAND flash with ECC support (1.8 V)
30 - CPLD connection: 8-bit registers in CPLD to configure mux/demux selections
31 - Support two 64 MB onboard QSPI NOR flash memories
[all …]
/Zephyr-latest/include/zephyr/drivers/i3c/
Dccc.h5 * SPDX-License-Identifier: Apache-2.0
117 /** Enter HDR Mode (HDR-DDR) (Broadcast) */
120 /** Enter HDR Mode 0 (HDR-DDR) (Broadcast) */
123 /** Enter HDR Mode 1 (HDR-TSP) (Broadcast) */
126 /** Enter HDR Mode 2 (HDR-TSL) (Broadcast) */
129 /** Enter HDR Mode 3 (HDR-BT) (Broadcast) */
171 /** Multi-Lane Data Transfer Control (Broadcast) */
243 * - For Write CCC, pointer to the byte array of data
244 * to be sent, which may contain the Sub-Command Byte
246 * - For Read CCC, pointer to the byte buffer for data
[all …]
/Zephyr-latest/boards/renesas/rzg3s_smarc/doc/
Dindex.rst6 The Renesas RZ/G3S SMARC Evaluation Board Kit (RZ/G3S-EVKIT) consists of a SMARC v2.1 module board …
10 * Cortex-A55 Single, Cortex-M33 x 2
11 * BGA 359-pin, 14mmSq body, 0.5mm pitch
29 * CAN-FD x2
33 * USB-Type C for power input
34 * PCIe Gen2 4-lane slot (G3S supports only 1-lane)
54 The ``rzg3s_smarc/r9a08g045s33gbg/cm33`` board target supports the ARM Cortex-M33 System Core witho…
57 +-----------+------------+-------------------------------------+
60 | NVIC | on-chip | arch/arm |
61 +-----------+------------+-------------------------------------+
[all …]
/Zephyr-latest/boards/element14/warp7/doc/
Dindex.rst6 The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7
7 core and Single Cortex M4 core.
19 - 6-axis Accelerometer Magnetometer: NXP FXOS8700CQ (I2C4 interface)
20 - 3-axis Gyroscope: NXP FXAS21002C (I2C4 interface)
21 - Altimeter: NXP MPL3115A2 (I2C4 interface)
22 - NXP NTAG NT3H1101 (I2C2 interface)
23 - Audio Codec: NXP SGTL5000 (I2C4 and SAI1 interfaces)
24 - S1 - Reset Button (POR_B signal)
25 - S2 - User Defined button (ENET1_RD1/GPIO7_IO1 signal)
26 - S3 - On/Off (MX7_ONOFF signal)
[all …]
/Zephyr-latest/boards/technexion/pico_pi/doc/
Dindex.rst6 The i.MX7D SoC is a Hybrid multi-core processor composed of Single Cortex A7
7 core and Single Cortex M4 core.
14 The Pico-Pi Platform is composed of a CPU and IO board.
16 Pico-Pi IO Board
18 - S1 - On/Off (MX7_ONOFF signal)
19 - Board to board connector : Edison compatible connector (70 configurable pins)
20 - mikroBUS expansion connector ADC, GPIO, I²C, PWM, SPI, UART)
21 - 10-pin needle JTAG Connector
22 - Debug USB exposing One UART
23 - MIPI DSI 1 lane Connector
[all …]
/Zephyr-latest/drivers/pcie/host/
Dshell.c4 * SPDX-License-Identifier: Apache-2.0
32 { PCI_CAP_ID_PCIX, "PCI-X" },
34 { PCI_CAP_ID_VNDR, "Vendor-Specific" },
37 { PCI_CAP_ID_SHPC, "PCI Standard Hot-Plug Controller" },
42 { PCI_CAP_ID_MSIX, "MSI-X" },
58 { PCIE_EXT_CAP_ID_MFVC, "Multi-Function VC Capability" },
61 { PCIE_EXT_CAP_ID_VNDR, "Vendor-Specific Extended Capability" },
62 { PCIE_EXT_CAP_ID_CAC, "Config Access Correlation - obsolete" },
64 { PCIE_EXT_CAP_ID_ARI, "Alternate Routing-ID Interpretation" },
66 { PCIE_EXT_CAP_ID_SRIOV, "Single Root I/O Virtualization" },
[all …]
/Zephyr-latest/include/zephyr/drivers/
Di3c.h5 * SPDX-License-Identifier: Apache-2.0
42 * - BCR[7:6]: Device Role
43 * - 0: I3C Target
44 * - 1: I3C Controller capable
45 * - 2: Reserved
46 * - 3: Reserved
48 * - BCR[5]: Advanced Capabilities
49 * - 0: Does not support optional advanced capabilities.
50 * - 1: Supports optional advanced capabilities which
53 * - BCR[4]: Virtual Target Support
[all …]