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/Zephyr-latest/drivers/flash/
Dflash_sam0.c4 * SPDX-License-Identifier: Apache-2.0
22 BUILD_ASSERT((FLASH_WRITE_BLK_SZ % sizeof(uint32_t)) == 0, "unsupported write-block-size");
84 struct flash_sam0_data *ctx = dev->data; in flash_sam0_sem_take()
86 k_sem_take(&ctx->sem, K_FOREVER); in flash_sam0_sem_take()
93 struct flash_sam0_data *ctx = dev->data; in flash_sam0_sem_give()
95 k_sem_give(&ctx->sem); in flash_sam0_sem_give()
99 static int flash_sam0_valid_range(off_t offset, size_t len) in flash_sam0_valid_range() argument
101 if (offset < 0) { in flash_sam0_valid_range()
102 LOG_WRN("0x%lx: before start of flash", (long)offset); in flash_sam0_valid_range()
103 return -EINVAL; in flash_sam0_valid_range()
[all …]
Dflash_rpi_pico.c5 * SPDX-License-Identifier: Apache-2.0
44 * github.com/raspberrypi/pico-bootrom/blob/master/bootrom/program_flash_generic.c
46 * github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/hardware_flash/flash.c
85 io_rw_32 *reg = (io_rw_32 *) (IO_QSPI_BASE + IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET); in __no_inline_not_in_flash_func() local
86 *reg = (*reg & ~IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS) in __no_inline_not_in_flash_func()
88 (void) *reg; in __no_inline_not_in_flash_func()
100 const uint max_in_flight = 16 - 2; in __no_inline_not_in_flash_func()
109 tx_level = ssi_hw->txflr; in __no_inline_not_in_flash_func()
110 rx_level = ssi_hw->rxflr; in __no_inline_not_in_flash_func()
113 ssi->dr0 = (uint32_t) (tx ? *tx++ : 0); in __no_inline_not_in_flash_func()
[all …]
/Zephyr-latest/drivers/bbram/
Dbbram_stm32.c4 * SPDX-License-Identifier: Apache-2.0
23 #define STM32_BKP_REG_OFFSET (TAMP_BASE + offsetof(TAMP_TypeDef, BKP0R) - RTC_BASE)
27 #define STM32_BKP_REG_INDEX(offset) ((offset) >> 2) argument
28 #define STM32_BKP_REG_BYTE_INDEX(offset) ((offset)&0x3UL) argument
29 #define STM32_BKP_REG(i) (((volatile uint32_t *)config->base_addr)[(i)])
40 static int bbram_stm32_read(const struct device *dev, size_t offset, size_t size, uint8_t *data) in bbram_stm32_read() argument
42 const struct bbram_stm32_config *config = dev->config; in bbram_stm32_read()
43 uint32_t reg, begin, to_copy; in bbram_stm32_read() local
45 if (size < 1 || offset + size > config->size) { in bbram_stm32_read()
46 return -EFAULT; in bbram_stm32_read()
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_pcr.h4 * SPDX-License-Identifier: Apache-2.0
53 * CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires
68 * Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP()
69 * Cortex-M4 will assert sleep signal to PCR block.
105 * Divides 96MHz clock to ARM Cortex-M4 core including
121 /* PCR Oscillator ID register (Read-Only) */
153 * Sleep Enable Reg 0 (Offset +30h)
154 * Clock Required Reg 0 (Offset +50h)
155 * Reset Enable Reg 0 (Offset +70h)
162 * Sleep Enable Reg 1 (Offset +34h)
[all …]
/Zephyr-latest/dts/bindings/mtd/
Dfixed-partitions.yaml9 compatible = "fixed-partitions";
10 #address-cells = <1>;
11 #size-cells = <1>;
15 reg = <0x00000000 0x0000C000>;
18 label = "image-0";
19 reg = <0x0000C000 0x00076000>;
22 label = "image-1";
23 reg = <0x00082000 0x00076000>;
37 reg = <0x000f8000 0x00008000>;
43 The fixed-partitions node should be a child of the flash
[all …]
/Zephyr-latest/drivers/sensor/ti/tmp116/
Dtmp116.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/sensor/tmp116.h>
28 static int tmp116_reg_read(const struct device *dev, uint8_t reg, in tmp116_reg_read() argument
31 const struct tmp116_dev_config *cfg = dev->config; in tmp116_reg_read()
33 if (i2c_burst_read_dt(&cfg->bus, reg, (uint8_t *)val, 2) in tmp116_reg_read()
35 return -EIO; in tmp116_reg_read()
43 static int tmp116_reg_write(const struct device *dev, uint8_t reg, in tmp116_reg_write() argument
46 const struct tmp116_dev_config *cfg = dev->config; in tmp116_reg_write()
47 uint8_t tx_buf[3] = {reg, val >> 8, val & 0xFF}; in tmp116_reg_write()
49 return i2c_write_dt(&cfg->bus, tx_buf, sizeof(tx_buf)); in tmp116_reg_write()
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dgd32-clocks-common.h4 * SPDX-License-Identifier: Apache-2.0
11 * Encode RCU register offset and configuration bit.
13 * - 0..5: bit number
14 * - 6..14: offset
15 * - 15: reserved
17 * @param reg RCU register name (expands to GD32_{reg}_OFFSET)
20 #define GD32_CLOCK_CONFIG(reg, bit) \ argument
21 (((GD32_ ## reg ## _OFFSET) << 6U) | (bit))
/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dgd32-common.h4 * SPDX-License-Identifier: Apache-2.0
11 * Encode RCU register offset and configuration bit.
13 * - 0..5: bit number
14 * - 6..14: offset
15 * - 15: reserved
17 * @param reg RCU register name (expands to GD32_{reg}_OFFSET)
20 #define GD32_RESET_CONFIG(reg, bit) \ argument
21 (((GD32_ ## reg ## _OFFSET) << 6U) | (bit))
/Zephyr-latest/tests/drivers/build_all/display/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
13 #include <zephyr/dt-bindings/led/led.h>
14 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
23 gpio-controller;
24 reg = <0xdeadbeef 0x1000>;
25 #gpio-cells = <0x2>;
30 compatible = "zephyr,mipi-dbi-spi";
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/Zephyr-latest/tests/drivers/smbus/smbus_emul/src/
Demul.c4 * SPDX-License-Identifier: Apache-2.0
38 uint8_t offset; member
51 sys_slist_prepend(&peripherals, &peripheral->node); in emul_register_smbus_peripheral()
59 if (peripheral->addr == addr) { in emul_get_smbus_peripheral()
72 if (peripheral->smbalert && !peripheral->smbalert_handled) { in peripheral_handle_smbalert()
82 LOG_DBG("Return own address: 0x%02x", found->addr); in peripheral_handle_smbalert()
84 io_area[PCH_SMBUS_HD0] = found->addr; in peripheral_handle_smbalert()
85 found->smbalert_handled = true; in peripheral_handle_smbalert()
95 if (peripheral->host_notify) { in peripheral_handle_host_notify()
97 io_area[PCH_SMBUS_NDA] = peripheral->addr << 1; in peripheral_handle_host_notify()
[all …]
/Zephyr-latest/dts/x86/intel/
Draptor_lake_p.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/pcie/pcie.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
21 reg = <0>;
[all …]
Delkhart_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,elkhart-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
21 reg = <0>;
28 reg = <0x0 DT_DRAM_SIZE>;
[all …]
Draptor_lake_s.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
21 reg = <0>;
[all …]
/Zephyr-latest/boards/shields/seeed_xiao_expansion_board/
Dseeed_xiao_expansion_board.overlay3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "gpio-keys";
34 reg = <0x3c>;
37 segment-offset = <0>;
38 page-offset = <0>;
39 display-offset = <0>;
40 multiplex-ratio = <63>;
41 segment-remap;
42 com-invdir;
[all …]
/Zephyr-latest/dts/bindings/pwm/
Dintel,blinky-pwm.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "intel,blinky-pwm"
9 include: [pwm-controller.yaml, base.yaml]
12 reg:
15 reg-offset:
18 description: PWM control register offset from base
20 clock-frequency:
25 max-pins:
30 "#pwm-cells":
33 pwm-cells:
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dintel,gpio.yaml1 # Copyright (c) 2018-2019 Intel Corporation
2 # SPDX-License-Identifier: Apache-2.0
8 include: [acpi.yaml, gpio-controller.yaml, base.yaml]
11 reg:
12 description: reg properties not required if acpi enumerated
14 group-index:
24 pin-offset:
26 description: Pin offset of this GPIO entry
28 "#gpio-cells":
31 gpio-cells:
[all …]
/Zephyr-latest/boards/nxp/mimxrt595_evk/
Dmimxrt595_evk_mimxrt595s_f1.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "cdns,tensilica-xtensa-lx6";
21 reg = <0>;
26 #address-cells = <1>;
27 #size-cells = <1>;
29 compatible = "mmio-sram";
31 reg = <0x0 DT_SIZE_K(512)>;
[all …]
/Zephyr-latest/dts/bindings/dma/
Dnxp,mcux-edma.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-edma"
8 include: dma-controller.yaml
11 reg:
20 dma-channels:
23 dma-requests:
26 dmamux-reg-offset:
30 The offset value for obtaining DMAMUX register index from DMAMUX channel.
33 channel-gap:
47 irq-shared-offset:
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_smsc911x_priv.h1 /* SPDX-License-Identifier: Apache-2.0 */
4 * Copyright (c) 2018-2019 Linaro Limited
10 * http://www.apache.org/licenses/LICENSE-2.0
25 /* This file is the re-implementation of mps2_ethernet_api and Selftest's
27 * MPS2 Selftest:https://silver.arm.com/browse/VEI10 ->
28 * \ISCM-1-0\AN491\software\Selftest\v2m_mps2\
44 (((val) >> (lsb)) & ((1 << ((msb) - (lsb) + 1)) - 1))
46 #define SMSC9220_BFIELD(reg, bfield) BFIELD(SMSC9220->reg, reg ## _ ## bfield) argument
53 /* Receive FIFO Ports (offset 0x0) */
56 /* Transmit FIFO Ports (offset 0x20) */
[all …]
/Zephyr-latest/drivers/mfd/
Dmfd_npm1300.c3 * SPDX-License-Identifier: Apache-2.0
62 uint8_t offset; member
87 k_work_submit(&data->work); in gpio_callback()
93 const struct mfd_npm1300_config *config = data->dev->config; in work_callback()
98 ret = mfd_npm1300_reg_read_burst(data->dev, MAIN_BASE, 0U, buf, sizeof(buf)); in work_callback()
100 k_work_submit(&data->work); in work_callback()
105 int offset = event_reg[i].offset + MAIN_OFFSET_CLR; in work_callback() local
107 if ((buf[offset] & event_reg[i].mask) != 0U) { in work_callback()
108 gpio_fire_callbacks(&data->callbacks, data->dev, BIT(i)); in work_callback()
110 ret = mfd_npm1300_reg_write(data->dev, MAIN_BASE, offset, in work_callback()
[all …]
/Zephyr-latest/arch/arc/include/
Dswap_macros.h1 /* swap_macros.h - helper macros for context switch */
6 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/arch/arc/tool-compat.h>
17 #include <zephyr/arch/arc/asm-compat/assembler.h>
280 * _kernel.current. r3 is a scratch reg.
362 * need two temp reg to do this
367 and MACRO_ARG(reg1), MACRO_ARG(reg1), ((1 << ARC_N_IRQ_START_LEVEL) - 1)
378 * the result will be in reg (a reg)
380 .macro _get_cpu_id, reg
381 LRR MACRO_ARG(reg), [_ARC_V2_IDENTITY]
[all …]
/Zephyr-latest/boards/shields/ssd1306/
Dssd1306_128x32.overlay4 * SPDX-License-Identifier: Apache-2.0
18 reg = <0x3c>;
21 segment-offset = <0>;
22 page-offset = <0>;
23 display-offset = <0>;
24 multiplex-ratio = <31>;
25 segment-remap;
26 com-invdir;
27 com-sequential;
Dsh1106_128x64.overlay4 * SPDX-License-Identifier: Apache-2.0
18 reg = <0x3c>;
21 segment-offset = <2>;
22 page-offset = <0>;
23 display-offset = <0>;
24 multiplex-ratio = <63>;
25 segment-remap;
26 com-invdir;
Dssd1306_128x64.overlay4 * SPDX-License-Identifier: Apache-2.0
18 reg = <0x3c>;
21 segment-offset = <0>;
22 page-offset = <0>;
23 display-offset = <0>;
24 multiplex-ratio = <63>;
25 segment-remap;
26 com-invdir;
/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_rcar.c2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
45 uint32_t offset; member
95 uint16_t reg_offs = PFC_RCAR_IPSR + rcar_func->bank * sizeof(uint32_t); in pfc_rcar_set_ipsr()
98 val &= ~(0xFU << rcar_func->shift); in pfc_rcar_set_ipsr()
99 val |= (rcar_func->func << rcar_func->shift); in pfc_rcar_set_ipsr()
103 static uint32_t pfc_rcar_get_drive_reg(uint16_t pin, uint8_t *offset, in pfc_rcar_get_drive_reg() argument
108 while (drive_regs->reg != 0U) { in pfc_rcar_get_drive_reg()
109 for (size_t i = 0U; i < ARRAY_SIZE(drive_regs->fields); i++) { in pfc_rcar_get_drive_reg()
110 if (drive_regs->fields[i].pin == pin) { in pfc_rcar_get_drive_reg()
[all …]

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