Lines Matching +full:reg +full:- +full:offset

1 /* SPDX-License-Identifier: Apache-2.0 */
4  * Copyright (c) 2018-2019 Linaro Limited
10  *     http://www.apache.org/licenses/LICENSE-2.0
25 /* This file is the re-implementation of mps2_ethernet_api and Selftest's
27  * MPS2 Selftest:https://silver.arm.com/browse/VEI10 ->
28  *     \ISCM-1-0\AN491\software\Selftest\v2m_mps2\
44 	(((val) >> (lsb)) & ((1 << ((msb) - (lsb) + 1)) - 1))
46 #define SMSC9220_BFIELD(reg, bfield) BFIELD(SMSC9220->reg, reg ## _ ## bfield)  argument
53 /*   Receive FIFO Ports (offset 0x0) */
56 /*   Transmit FIFO Ports (offset 0x20) */
60 /*   Receive FIFO status port (offset 0x40) */
62 /*   Receive FIFO status peek (offset 0x44) */
64 /*   Transmit FIFO status port (offset 0x48) */
66 /*   Transmit FIFO status peek (offset 0x4C) */
69 /*   Chip ID and Revision (offset 0x50) */
71 /*   Main Interrupt Configuration (offset 0x54) */
73 /*   Interrupt Status (offset 0x58) */
75 /*   Interrupt Enable Register (offset 0x5C) */
77 /*   Reserved for future use (offset 0x60) */
79 /*   Read-only byte order testing register 87654321h (offset 0x64) */
81 /*   FIFO Level Interrupts (offset 0x68) */
83 /*   Receive Configuration (offset 0x6C) */
85 /*   Transmit Configuration (offset 0x70) */
87 /*   Hardware Configuration (offset 0x74) */
89 /*   RX Datapath Control (offset 0x78) */
91 /*   Receive FIFO Information (offset 0x7C) */
93 /*   Transmit FIFO Information (offset 0x80) */
95 /*   Power Management Control (offset 0x84) */
97 /*   General Purpose IO Configuration (offset 0x88) */
99 /*   General Purpose Timer Configuration (offset 0x8C) */
101 /*   General Purpose Timer Count (offset 0x90) */
103 /*   Reserved for future use (offset 0x94) */
105 /*   WORD SWAP Register (offset 0x98) */
107 /*   Free Run Counter (offset 0x9C) */
109 /*   RX Dropped Frames Counter (offset 0xA0) */
111 /*   MAC CSR Synchronizer Command (offset 0xA4) */
113 /*   MAC CSR Synchronizer Data (offset 0xA8) */
115 /*   Automatic Flow Control Configuration (offset 0xAC) */
117 /*   EEPROM Command (offset 0xB0) */
119 /*   EEPROM Data (offset 0xB4) */
207 	/* 26 - 30 Reserved according to Datasheet*/