Lines Matching +full:reg +full:- +full:offset

4  * SPDX-License-Identifier: Apache-2.0
53  * CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires
68  * Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP()
69  * Cortex-M4 will assert sleep signal to PCR block.
105  * Divides 96MHz clock to ARM Cortex-M4 core including
121 /*  PCR Oscillator ID register (Read-Only) */
153  * Sleep Enable Reg 0 (Offset +30h)
154  * Clock Required Reg 0 (Offset +50h)
155  * Reset Enable Reg 0 (Offset +70h)
162  * Sleep Enable Reg 1 (Offset +34h)
163  * Clock Required Reg 1 (Offset +54h)
164  * Reset Enable Reg 1 (Offset +74h)
192  * Sleep Enable Reg 2 (Offset +38h)
193  * Clock Required Reg 2 (Offset +58h)
194  * Reset Enable Reg 2 (Offset +78h)
216  * Sleep Enable Reg 3 (Offset +3Ch)
217  * Clock Required Reg 3 (Offset +5Ch)
218  * Reset Enable Reg 3 (Offset +7Ch)
247  * Sleep Enable Reg 4 (Offset +40h)
248  * Clock Required Reg 4 (Offset +60h)
249  * Reset Enable Reg 4 (Offset +80h)
268 /* Reset Enable Lock (Offset +84h) */
272 /* VBAT Soft Reset (Offset +88h) */
276 /* VTR Source 32 KHz Clock (Offset +8Ch) */
284  * Clock monitor 32KHz period counter (Offset +C0h, RO)
285  * Clock monitor 32KHz high counter (Offset +C4h, RO)
286  * Clock monitor 32KHz period counter minimum (Offset +C8h, RW)
287  * Clock monitor 32KHz period counter maximum (Offset +CCh, RW)
288  * Clock monitor 32KHz Duty Cycle variation counter (Offset +D0h, RO)
289  * Clock monitor 32KHz Duty Cycle variation counter maximum (Offset +D4h, RW)
294  * Clock monitor 32KHz Valid Count (Offset +0xD8, RO)
295  * Clock monitor 32KHz Valid Count minimum (Offset +0xDC, RW)
299 /* Clock monitor control register (Offset +0xE0, RW) */
307 /* Clock monitor interrupt status (Offset +0xE4, R/W1C) */
317 /* Clock monitor interrupt enable (Offset +0xE8, RW) */
350 	uint32_t RSVD4[(0x00c0 - 0x0094) / 4];