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Searched +full:qspi +full:- +full:nor (Results 1 – 25 of 140) sorted by relevance

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/Zephyr-latest/drivers/flash/
DKconfig.nordic_qspi_nor2 # SPDX-License-Identifier: Apache-2.0
5 bool "QSPI NOR Flash"
15 Enable support for nrfx QSPI driver with EasyDMA.
34 int "Size of a stack-based buffer to handle writes not supported by QSPI"
37 The QSPI peripheral uses DMA and can only write data that is read
38 from a word-aligned location in RAM. A non-zero value here enables
49 Enable setting up the QSPI NOR driver to allow for execution of code
50 stored in QSPI XIP region. Note that for this functionality to work,
51 the QSPI NOR init priority must be set so that no XIP code in the
52 QSPI NOR flash chip is executed until the driver has been setup.
[all …]
DKconfig.npcx_fiu4 # SPDX-License-Identifier: Apache-2.0
7 bool "Nuvoton NPCX QSPI Bus Flash driver"
12 This option enables the QSPI Bus Flash driver for NPCX family of
16 bool "Nuvoton NPCX embedded controller (EC) QSPI NOR Flash driver"
26 This option enables the QSPI NOR Flash driver for NPCX family of
32 bool "QSPI NOR flash feature during driver initialization"
36 This option enables the QSPI NOR Flash features such as Quad-Enable,
37 4-byte address support and so on during driver initialization. Disable
38 it if QSPI NOR devices are not ready during driver initialization.
66 Read Access (DRA) on QSPI bus.
DKconfig.cadence_qspi_nor2 # SPDX-License-Identifier: Apache-2.0
12 Enable Cadence QSPI-NOR support.
29 int "Access QSPI address memory size in bytes"
33 accessing QSPI.
36 int "Set QSPI to read / write how many bytes per device"
39 Set the size for a QSPI to read / write per device.
42 int "Set QSPI to read / write how many bytes per block"
45 Set the size for a QSPI to read / write per block.
DKconfig.nxp_s322 # SPDX-License-Identifier: Apache-2.0
5 bool "NXP S32 QSPI NOR driver"
14 Enable the Flash driver for a NOR Serial Flash Memory device connected
15 to an NXP S32 QSPI bus.
24 JESD216-compatible devices, with the following notes:
25 - Quad Enable Requirements bitfield (DW15) must be present in the SFDP
28 - Soft Reset bitfield (DW16) must be present in the SFDP tables to
30 - 0-X-X mode discovery not yet implemented by the HAL.
34 device size and jedec-id properties must be set in devicetree node.
51 By default the page size corresponds to the sector size (4096) for a NOR
[all …]
/Zephyr-latest/dts/bindings/flash_controller/
Dnuvoton,npcx-fiu-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The SPI NOR flash devices accessed by Nuvoton Flash Interface Unit (FIU).
7 Representation of a SPI NOR flash on a qspi bus looks like:
10 compatible ="nuvoton,npcx-fiu-nor";
14 qspi-flags = <NPCX_QSPI_SW_CS1>;
15 mapped-addr = <0x64000000>;
16 pinctrl-0 = <&int_flash_sl>;
17 pinctrl-names = "default";
20 compatible: "nuvoton,npcx-fiu-nor"
22 include: [flash-controller.yaml, pinctrl-device.yaml, "jedec,spi-nor-common.yaml"]
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Dst,stm32-qspi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 QSPI Flash controller supporting the JEDEC CFI interface
9 mx25r6435f: qspi-nor-flash@90000000 {
10 compatible = "st,stm32-qspi-nor";
12 qspi-max-frequency = <80000000>;
13 reset-gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
14 reset-gpios-duration = <1>;
15 spi-bus-width = <4>;
19 compatible: "st,stm32-qspi-nor"
21 include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
[all …]
Dcdns,qspi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Cadence Quad-SPI NOR flash controller
6 compatible: "cdns,qspi-nor"
8 include: flash-controller.yaml
11 clock-frequency:
14 description: clock frequency information for Cadence QSPI NOR Flash
Daltr,nios2-qspi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Altera NIOS2 QSPI Flash controller supporting the JEDEC CFI interface
6 compatible: "altr,nios2-qspi-nor"
8 include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
10 on-bus: qspi
/Zephyr-latest/samples/drivers/spi_flash/
DREADME.rst1 .. zephyr:code-sample:: spi-nor
2 :name: JEDEC SPI-NOR flash
3 :relevant-api: flash_interface
5 Use the flash API to interact with an SPI NOR serial flash memory device.
10 This sample demonstrates using the :ref:`flash API <flash_api>` on a SPI NOR serial flash
21 * :dtcompatible:`jedec,spi-nor`,
22 * :dtcompatible:`st,stm32-qspi-nor`,
23 * :dtcompatible:`st,stm32-ospi-nor`,
24 * :dtcompatible:`nordic,qspi-nor`.
26 .. zephyr-app-commands::
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Dsample.yaml6 - spi
7 - flash
8 filter: dt_compat_enabled("jedec,spi-nor") or dt_compat_enabled("st,stm32-qspi-nor")
9 or dt_compat_enabled("st,stm32-ospi-nor") or dt_compat_enabled("st,stm32-xspi-nor")
10 or (dt_compat_enabled("nordic,qspi-nor") and CONFIG_NORDIC_QSPI_NOR)
12 - hifive_unmatched/fu740/s7
13 - hifive_unmatched/fu740/u74
19 - "Test 1: Flash erase"
20 - "Flash erase succeeded!"
21 - "Test 2: Flash write"
[all …]
/Zephyr-latest/dts/bindings/mtd/
Dandestech,qspi-nor.yaml4 # SPDX-License-Identifier: Apache-2.0
7 compatible: "andestech,qspi-nor"
10 Properties supporting Zephyr qspi-nor flash driver control of
11 flash memories using the standard M25P80-based command set.
13 include: "jedec,spi-nor-common.yaml"
16 wp-gpios:
17 type: phandle-array
20 hold-gpios:
21 type: phandle-array
24 reset-gpios:
[all …]
Dnxp,s32-qspi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
5 QSPI NOR flash connected to the NXP S32 QSPI bus.
7 compatible: "nxp,s32-qspi-nor"
9 include: "nxp,s32-qspi-device.yaml"
12 has-32k-erase:
20 - "1-1-1" # 0x0B
21 - "1-1-2" # 0x3B
22 - "1-2-2" # 0xBB
23 - "1-1-4" # 0x6B
24 - "1-4-4" # 0xEB
[all …]
Dnordic,qspi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
5 QSPI NOR flash supporting the JEDEC CFI interface.
7 compatible: "nordic,qspi-nor"
9 include: [base.yaml, "jedec,spi-nor-common.yaml"]
11 on-bus: qspi
17 jedec-id:
23 The size in bits. Set this or size-in-bytes, but not both.
25 size-in-bytes:
31 quad-enable-requirements:
37 - "fastread" # Single data line SPI, FAST_READ (0x0B)
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/Zephyr-latest/samples/subsys/fs/littlefs/boards/
Dnucleo_h743zi.overlay5 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &storage_partition;
11 pinctrl-0 = <&sdmmc1_d0_pc8
15 pinctrl-names = "default";
23 read-size = <32>;
24 prog-size = <32>;
25 cache-size = <256>;
26 lookahead-size = <64>;
27 block-cycles = <512>;
29 mount-point = "/lfs1";
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/Zephyr-latest/samples/drivers/jesd216/
Dsample.yaml5 - spi
6 - flash
12 - "sfdp-bfp ="
13 - "jedec-id ="
17 - hifive1
18 - hifive_unleashed/fu540/e51
19 - hifive_unleashed/fu540/u54
20 - hifive_unmatched/fu740/s7
21 - hifive_unmatched/fu740/u74
22 - mimxrt1170_evk/mimxrt1176/cm7
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/Zephyr-latest/samples/subsys/usb/mass/
Dsample.yaml9 - EXTRA_DTC_OVERLAY_FILE="ramdisk.overlay"
11 - CONFIG_LOG_DEFAULT_LEVEL=3
13 - msd
14 - usb
20 - "No file system selected"
21 - "The device is put in USB mass storage mode."
26 - nrf52840dk/nrf52840
27 - nrf54h20dk/nrf54h20/cpuapp
28 - frdm_k64f
29 - stm32f723e_disco
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/Zephyr-latest/boards/shields/v2c_daplink/doc/
Dindex.rst3 ARM V2C-DAPLink for DesignStart FPGA
9 The `ARM V2C-DAPLink for DesignStart FPGA`_ shield can be used to provide
15 :alt: V2C-DAPLink
17 V2C-DAPLink (Credit: ARM Ltd.)
19 In addition to DAPLink debug access, the V2C-DAPLink shield provides the
22 - QSPI NOR flash
23 - Micro-SD card slot
28 When using the V2C-DAPLink shield with the ``Cfg`` jumper (``J2``) open, the CPU
32 .. zephyr-app-commands::
33 :zephyr-app: samples/hello_world
[all …]
/Zephyr-latest/include/zephyr/drivers/flash/
Dnpcx_flash_api_ex.h4 * SPDX-License-Identifier: Apache-2.0
22 * configuration such as status registers of nor flash, power on/off,
27 * NPCX Configure specific operation for Quad-SPI nor flash.
29 * It configures specific operation for Quad-SPI nor flash such as lock
35 * NPCX Get specific operation for Quad-SPI nor flash.
37 * It returns current specific operation for Quad-SPI nor flash.
67 /* Specific NPCX QSPI devices control bits */
/Zephyr-latest/samples/drivers/jesd216/boards/
Dnrf52840dk_nrf52840_spi.overlay2 * Copyright (c) 2022-2023 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &mx25r64;
9 &qspi {
14 * to provide quad-spi feature. In individual specifications each of the spi
16 * as qspi configuration, which is pin (0,19). That is why spi2 is used here
17 * to communicate with mx25, when qspi is not used, to avoid rerouting clock
21 compatible = "nordic,nrf-spi";
23 cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
24 pinctrl-0 = <&spi2_default>;
[all …]
/Zephyr-latest/boards/st/stm32h745i_disco/
Dstm32h745i_disco_stm32h745xx_m7.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
13 model = "STMicroelectronics STM32H745I-DISCO board";
14 compatible = "st,stm32h745i-disco";
19 zephyr,shell-uart = &usart3;
23 zephyr,flash-controller = &mt25ql512ab1;
28 compatible = "pwm-leds";
32 label = "User LD8 - PWM11";
36 /* RM0455 - 23.6 External device address mapping */
38 compatible = "zephyr,memory-region", "mmio-sram";
[all …]
/Zephyr-latest/boards/altr/max10/
Daltera_max10.dts1 /* SPDX-License-Identifier: Apache-2.0 */
4 /dts-v1/;
11 compatible = "altr,nios2-max10";
14 uart-0 = &uart0;
21 zephyr,shell-uart = &uart0;
27 current-speed = <115200>;
32 clock-frequency = <I2C_BITRATE_ULTRA>;
35 &qspi {
38 compatible = "altr,nios2-qspi-nor";
/Zephyr-latest/dts/arm/nuvoton/
Dnpcx4m3f.dtsi4 * SPDX-License-Identifier: Apache-2.0
20 compatible = "mmio-sram";
24 soc-id {
25 device-id = <0x25>;
33 compatible ="nuvoton,npcx-fiu-nor";
38 /* quad spi bus configuration of nor flash device */
39 qspi-flags = <NPCX_QSPI_SW_CS0>;
40 mapped-addr = <0x60000000>;
Dnpcx4m8f.dtsi4 * SPDX-License-Identifier: Apache-2.0
20 compatible = "mmio-sram";
24 soc-id {
25 device-id = <0x23>;
33 compatible ="nuvoton,npcx-fiu-nor";
38 /* quad spi bus configuration of nor flash device */
39 qspi-flags = <NPCX_QSPI_SW_CS0>;
40 mapped-addr = <0x60000000>;
/Zephyr-latest/boards/st/stm32h750b_dk/
Dstm32h750b_dk.dts2 * Copyright (c) 2023-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h750xbhx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "st,stm32h750b-dk";
19 zephyr,shell-uart = &usart3;
22 zephyr,flash-controller = &mt25ql512ab1;
27 compatible = "zephyr,memory-region", "mmio-sram";
30 zephyr,memory-region = "SDRAM2";
[all …]
/Zephyr-latest/boards/st/stm32h747i_disco/
Dstm32h747i_disco_stm32h747xx_m7.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h747xihx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15 compatible = "st,stm32h747i-disco";
20 zephyr,shell-uart = &usart1;
23 zephyr,flash-controller = &mt25ql512ab1;
27 compatible = "zephyr,memory-region", "mmio-sram";
30 zephyr,memory-region = "SDRAM2";
31 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
[all …]

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