Lines Matching +full:qspi +full:- +full:nor
2 * Copyright (c) 2023-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h750xbhx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "st,stm32h750b-dk";
19 zephyr,shell-uart = &usart3;
22 zephyr,flash-controller = &mt25ql512ab1;
24 zephyr,code-partition = &slot0_partition;
28 compatible = "zephyr,memory-region", "mmio-sram";
31 zephyr,memory-region = "SDRAM2";
32 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
36 compatible = "zephyr,memory-region";
38 zephyr,memory-region = "EXTMEM";
40 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
44 compatible = "gpio-leds";
56 compatible = "gpio-keys";
68 die-temp0 = &die_temp;
73 clock-frequency = <DT_FREQ_M(25)>;
74 hse-bypass;
84 compatible = "fixed-partitions";
85 #address-cells = <1>;
86 #size-cells = <1>;
96 pinctrl-0 = <<dc_r0_pi15 <dc_r1_pj0 <dc_r2_pj1 <dc_r3_ph9
103 pinctrl-names = "default";
105 disp-on-gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>;
107 ext-sdram = <&sdram2>;
115 pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
116 display-timings {
117 compatible = "zephyr,panel-timing";
118 de-active = <1>;
119 pixelclk-active = <0>;
120 hsync-active = <0>;
121 vsync-active = <0>;
122 hsync-len = <1>;
123 vsync-len = <10>;
124 hback-porch = <43>;
125 vback-porch = <12>;
126 hfront-porch = <8>;
127 vfront-porch = <4>;
129 def-back-color-red = <0xFF>;
130 def-back-color-green = <0xFF>;
131 def-back-color-blue = <0xFF>;
135 div-m = <5>;
136 mul-n = <192>;
137 div-p = <2>;
138 div-q = <4>;
139 div-r = <4>;
145 div-m = <5>;
146 mul-n = <192>;
147 div-p = <2>;
148 div-q = <20>;
149 div-r = <99>;
156 clock-frequency = <DT_FREQ_M(480)>;
166 pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
167 pinctrl-names = "default";
168 current-speed = <115200>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&quadspi_clk_pf10 &quadspi_bk1_ncs_pg6
179 dual-flash;
184 mt25ql512ab1: qspi-nor-flash-1@90000000 {
185 compatible = "st,stm32-qspi-nor";
187 qspi-max-frequency = <72000000>;
188 spi-bus-width = <4>;
189 reset-cmd;
193 compatible = "fixed-partitions";
194 #address-cells = <1>;
195 #size-cells = <1>;
198 label = "image-0";
203 label = "image-1";
214 mt25ql512ab2: qspi-nor-flash-2@90000000 {
215 compatible = "st,stm32-qspi-nor";
217 qspi-max-frequency = <72000000>;
223 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
234 pinctrl-names = "default";
239 power-up-delay = <100>;
240 num-auto-refresh = <8>;
241 mode-register = <0x230>;
242 refresh-rate = <0x603>;
245 st,sdram-control = <STM32_FMC_SDRAM_NC_8
253 st,sdram-timing = <2 7 4 7 2 2 2>;
269 st,adc-clock-source = "SYNC";
270 st,adc-prescaler = <4>;
277 dma-names = "tx", "rx";
278 pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
279 pinctrl-names = "default";
280 current-speed = <115200>;